Table of Contents
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Interrupt Enable Set Register ................................................................................................................. 40–35
Polynomial Register ............................................................................................................................... 40–36
CRC Current Result Register ................................................................................................................ 40–37
CRC Final Result Register ..................................................................................................................... 40–38
Status Register ....................................................................................................................................... 40–39
Housekeeping ADC (HADC)
HADC Features ........................................................................................................................................... 41–1
HADC Functional Description.................................................................................................................... 41–1
ADSP-SC58x HADC Register List........................................................................................................... 41–2
ADSP-SC58x HADC Interrupt List ........................................................................................................ 41–2
ADSP-SC58x HADC Trigger List ............................................................................................................ 41–2
HADC Definitions................................................................................................................................... 41–3
HADC Block Diagram ............................................................................................................................. 41–4
HADC Signal Descriptions ...................................................................................................................... 41–5
HADC Architectural Concepts................................................................................................................. 41–5
Converter Operation ............................................................................................................................. 41–5
Auto-Scan.............................................................................................................................................. 41–6
Channel Sequence Programming........................................................................................................... 41–7
ADC Transfer Function......................................................................................................................... 41–7
Results................................................................................................................................................... 41–7
HADC Operating Modes ............................................................................................................................ 41–7
HADC Event Control.................................................................................................................................. 41–8
HADC Programming Model ....................................................................................................................... 41–8
ADSP-SC58x HADC Register Descriptions ............................................................................................... 41–8
Channel Mask Register .......................................................................................................................... 41–10
Control Register .................................................................................................................................... 41–11
Channel Data Registers ......................................................................................................................... 41–13
Interrupt Mask Register ......................................................................................................................... 41–14
Status Register ....................................................................................................................................... 41–15
xc
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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