Table 14-13: PORT_DIR_CLR Register Fields (Continued)
Bit No.
(Access)
1
PX1
(R/W1C)
0
PX0
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Port x Bit 1 Direction Clear.
The PORT_DIR_CLR.PX1 bit disables output mode and the output drivers for port
x.
Port x Bit 0 Direction Clear.
The PORT_DIR_CLR.PX0 bit disables output mode and the output drivers for port
x.
ADSP-SC58x PORT Register Descriptions
Description/Enumeration
0 No Effect
1 Disable output mode/driver
0 No Effect
1 Disable output mode/driver
14–35