Analog Devices ADSP-SC58 Series Hardware Reference Manual page 489

SMC Programmable Timing Characteristics
Figure 11-2: Basic Asynchronous SRAM Write Followed by Read
For the current bank, the programmed time cycles are:
• Write setup time = 2 cycles
• Write access time = 4 cycles
• Write hold time is = 2 cycles
• Read setup time = 3 cycles
• Read access time = 5 cycles
• Read hold time = 1 cycle
• Turnaround transition time = 2 cycles
• Idle transition time = 0 cycles
The asynchronous SRAM bus cycles proceed as follows.
1. At the start of the write setup period, the chip select signal (SMC_AMS[n]) for the target bank is asserted. The
write data (WD0), address (AW0), and byte enables become valid.
2. At the end of the setup phase and at the start of the write access period, the write enable (SMC_AWE) is asser-
ted.
3. At the end of the programmed write access, the SMC_AWE signal is deasserted. The target device is assumed to
have captured the write data before SMC_AWE is deasserted.
4. At the end of the write hold period, the SMC_AWE signal is deasserted because the pending access is a read
access, and the turnaround transition time cycles start. The write data and byte enables become invalid within
1 cycle of the SMC_AMS0 signal deasserting.
5. At the end of turnaround transition time, the read setup period starts with the assertion of the SMC_AMS0 and
SMC_AOE signals and a new read address (AR0) is presented on the address bus.
11–8
Write Write
Setup Access
2 Cycles 4 Cycles
CLKOUT
AW0
SMC_An
SMC_AMSn
SMC_AOE
SMC_AWE
SMC_ARE
BE1-0
00
SMC_D15-0
WD0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Write Trams Read Read
Hold TURN Setup Access
2 Cycles 2 Cycles 3 Cycles 5 Cycles
AR0
Read
Hold
1 Cycle
RD0