ADSP-SC58x SMC Register Descriptions
Table 11-6: SMC_B1CTL Register Fields (Continued)
Bit No.
(Access)
5:4
MODE
(R/W)
0
EN
(R/W)
11–28
Bit Name
Memory Access Mode.
The SMC_B1CTL.MODE bits select the protocol the SMC uses for static memory
read/write access. Note that the write protocol for async flash, async flash page, and
sync burst flash are all similar; only the read protocols differ for these modes.
Bank 1 Enable.
The SMC_B1CTL.EN bit enables accesses to the memory in bank 1. When this bit is
disabled, accesses to bank 1 return an error response.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Async SRAM protocol
1 Async flash protocol
2 Async flash page protocol
3 Reserved
0 Disable access
1 Enable access