Analog Devices ADSP-SC58 Series Hardware Reference Manual page 247

SEC Functional Description
• Slave control port which provides access to all SEC registers for configuration, status, and interrupt or fault
service model.
• Global locking supports a register level protection model to prevent writes to "locked" registers.
SEC Functional Description
The following sections provide a functional description of the SEC.
The SEC/GIC Interrupt Signal Flow figure shows an overview of the interrupt systems.
GENERIC
INTERRUPT
CONTROL (GIC)
ARM PL390
Figure 7-1: SEC/GIC Interrupt Signal Flow
ADSP-SC58x SEC Register List
The System Event Controller (SEC) manages the system fault sources, including control features such as enable/
disable, priority, and active/pending source status. For more information on SEC functionality, see the SEC register
descriptions.
Table 7-1: ADSP-SC58x SEC Register List
Name
SEC_CACT[n]
SEC_CCTL[n]
SEC_CGMSK[n]
SEC_CPLVL[n]
SEC_CPMSK[n]
SEC_CPND[n]
SEC_CSID[n]
SEC_CSTAT[n]
SEC_END
7–2
CORE1
SHARC
CORE0
ARM Cortex A5
SYSTEM CORE1
I/F (SCI)
CPU PORT
DISTRIBUTOR
PORT
Description
SCI Active Register n
SCI Control Register n
SCI Group Mask Register n
SCI Priority Level Register n
SCI Priority Mask Register n
Core Pending Register n
SCI Source ID Register n
SCI Status Register n
Global End Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DELAYED/FAULT ACTION
CONFIGURATIONS
--SYS_FAULT pin
--SYS EVENT FAULT INTERRUPT
--HW RESET
SYSTEM FAULT
I/F (SFI)
SYSTEM SOURCE
I/F (SSI)
SYSTEM EVENT CONTROLLER (SEC)
SCB BUS
CORE2
SHARC
SYSTEM CORE2
I/F (SCI)