Analog Devices ADSP-SC58 Series Hardware Reference Manual page 260

Sharc+ processor
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to the core. The SCI maintains the coherency for the system event service model implemented on the connected
core.
Figure 7-4: SCI Overview Block Diagram
SEC Source Interface (SSI)
The SSI manages all of the system event sources. It maintains the status of each source in the corresponding
SEC_SSTAT[n]
register. The corresponding
pending and enabled event passes its indication and priority to the SCI to which it is assigned for further processing.
Figure 7-5: SSI Overview Block Diagram
SEC Architectural Concepts
The following sections describe SEC architectural features.
System Interrupt Acknowledge
A system interrupt acknowledge occurs when the core provides an indication that it has acquired the SID of the
interrupt last issued by the SEC. The SEC core interface option allows generation by:
• A slave port write to the
• The assertion of an input acknowledge signal (the connected core generates the signal).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC Core Interface (SCI)
CPMSK
CPLVL
IDLE
INT
SID
CSID
ACK
NMI
SEC_SCTL[n]
SEC Source Interface (SSI)
SCTL0
SCTLn
SEC_CSID[n]
register.
CPND
CACT
SPR
CGMSK
CCTL
register manages the control of each source. A
SSTAT0
Source 0
SSTATn
Source n
SEC Block Diagram
S
S
I
NMI
7–15

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