Analog Devices ADSP-SC58 Series Hardware Reference Manual page 48

EPn Transmit Polling Interval Register ................................................................................................ 27–139
EPn Transmit Maximum Packet Length Register ................................................................................ 27–140
EPn Transmit Type Register ................................................................................................................ 27–141
EPn Number of Bytes Received Register .............................................................................................. 27–143
EPn Receive Configuration and Status (Host) Register ........................................................................ 27–144
EPn Receive Configuration and Status (Peripheral) Register ................................................................ 27–149
EPn Receive Polling Interval Register .................................................................................................. 27–154
EPn Receive Maximum Packet Length Register ................................................................................... 27–155
EPn Receive Type Register ................................................................................................................... 27–156
EPn Transmit Configuration and Status (Host) Register ..................................................................... 27–158
EPn Transmit Configuration and Status (Peripheral) Register ............................................................. 27–162
EPn Transmit Polling Interval Register ................................................................................................ 27–166
EPn Transmit Maximum Packet Length Register ................................................................................ 27–167
EPn Transmit Type Register ................................................................................................................ 27–168
Function Address Register ................................................................................................................... 27–170
FIFO Byte (8-Bit) Register .................................................................................................................. 27–171
FIFO Half-Word (16-Bit) Register ...................................................................................................... 27–172
FIFO Word (32-Bit) Register ............................................................................................................... 27–173
Frame Number Register ....................................................................................................................... 27–174
Full-Speed EOF 1 Register .................................................................................................................. 27–175
High-Speed EOF 1 Register ................................................................................................................. 27–176
ID Control .......................................................................................................................................... 27–177
Common Interrupts Enable Register ................................................................................................... 27–178
Index Register ...................................................................................................................................... 27–180
Receive Interrupt Register ................................................................................................................... 27–181
Receive Interrupt Enable Register ........................................................................................................ 27–184
Transmit Interrupt Register ................................................................................................................. 27–187
Transmit Interrupt Enable Register ..................................................................................................... 27–190
Common Interrupts Register ............................................................................................................... 27–193
Link Information Register ................................................................................................................... 27–195
xlviii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference