Analog Devices ADSP-SC58 Series Hardware Reference Manual page 287

ADSP-SC58x SEC Register Descriptions
Fault Delay Register
The SEC fault delay register (SEC_FDLY) contains the number (SEC_FDLY.COUNT field) of (SEC) clock peri-
ods to delay from fault pending to fault active, when actions are enabled.
COUNT[31:16] (R/W)
Fault Delay
Figure 7-18: SEC_FDLY Register Diagram
Table 7-17: SEC_FDLY Register Fields
Bit No.
(Access)
31:0 COUNT
(R/W)
7–42
15
0
COUNT[15:0] (R/W)
Fault Delay
31
0
Bit Name
Fault Delay.
The SEC_FDLY.COUNT bit field is the number of (SEC) clock periods to delay from
fault pending to fault active, when actions are enabled.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0