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• Direct mapped to 8-way associativity (fixed)
• Prefetching capability
• Event monitoring
• Software option to enable exclusive cache configuration
• Additional Buffers:
• Line Fill Buffers (LFBs)
• Line Read Buffers (LRBs)
• Eviction Buffers (EBs)
• Store Buffers (STBs)
• TrustZone support, with the following features:
• Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as an address bit. The
NS-tag bit is added in all buffers.
• NS bit in Tag RAM used to determine security level of evictions to L3.
• Restrictions for NS accesses for control, configuration, and maintenance registers to restrict access to se-
cure data.
• Parity Support
The L2CC Address Filtering registers should not be programmed by user. Not retaining the reset values
NOTE:
can give unpredictable results.
Sharing L2 Cache with SHARC+ Cores
The L2CC (PL310) supports two master and two slave ports. The SHARC+ core can access the L2-Cache without
bank conflict versus the Cortex A5 core by programming the L2CC registers. The cache access is restricted to the
address range: from CMMR_L2CC_START [31:0] to CMMR_L2CC_END [31:0]. For more information, see the
SHARC+ Core Programming Reference.
NOTE:
There is no guarantee for the data coherency between A5 and SHARC+ cores.
Programs should perform L2 cache write-back invalidation before changing the value of
NOTE:
CMMR_L2CC_START and CMMR_L2CC_END.
Floating-Point Unit (FPU)
The Cortex-A5 FPU is a VFPv4-D16 implementation of the ARMv7 floating-point architecture. It provides low-
cost high performance floating-point computation. The FPU supports all addressing modes and operations descri-
bed in the ARM Architecture Reference Manual.
The features in the FPU are as follows.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Functional Description
2–5
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