Table of Contents
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Data Transmit ........................................................................................................................................ 26–23
Data Receive........................................................................................................................................... 26–25
Data Transfer Commands....................................................................................................................... 26–27
Transmission and Reception with Internal DMAC (IDMAC) ................................................................ 26–27
MSI Event Control .................................................................................................................................... 26–27
MSI Status and Error Signals.................................................................................................................. 26–28
MSI Programming Model.......................................................................................................................... 26–30
MSI Programming Concepts .................................................................................................................. 26–30
Initializing the MSI ................................................................................................................................ 26–31
Enumerating the Card Stack................................................................................................................... 26–32
Identifying Card Types ........................................................................................................................... 26–33
Programming Card Clocks ..................................................................................................................... 26–34
Sending Non-Data Commands With or Without a Response Sequence ................................................. 26–35
Single-Block or Multiple-Block Read...................................................................................................... 26–36
Single-Block or Multiple-Block Write ..................................................................................................... 26–38
Stream Reads and Writes ........................................................................................................................ 26–39
Packed Commands ................................................................................................................................. 26–39
Sending Stop or Abort in Middle of Transfer.......................................................................................... 26–40
Suspend or Resume Sequence ................................................................................................................. 26–41
Read Wait Sequence ............................................................................................................................... 26–43
Card Read Threshold.............................................................................................................................. 26–43
MSI Programming Model, Boot Operation ............................................................................................... 26–45
Normal Boot Operation ......................................................................................................................... 26–45
Normal Boot Operation; eMMC......................................................................................................... 26–45
Normal Boot Operation; Removable MMC4.3, MMC4.4, and MMC4.41 Cards ............................. 26–47
Alternate Boot Operation; eMMC.......................................................................................................... 26–48
Alternate Boot Operation; Removable MMC4.3 Card ........................................................................... 26–51
ADSP-SC58x Product Specific Information .............................................................................................. 26–52
ADSP-SC58x MSI Register Descriptions .................................................................................................. 26–52
Block Size Register ................................................................................................................................. 26–54
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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