Table of Contents
Advertisement
CDU Programming Model
Figure 4-7: CDU Clock Options Link Port
The MSI clock can operate at up to 52 MHz for MMC/eMMC operation. The MSI clock can be selected from
CGU1 when the OCLK from CGU0 cannot be used.
Figure 4-8: CDU Clock Options MSI
CDU Programming Model
The
registers are a system configuration resource. These registers are accessed by a system configura-
CDU_CFG[n]
tion routine that also handles the configuration of other system modules. Writes to a
occur when there is not a CDU_CLKOn configuration change in progress. If a CGUn inputs are selected, that
CGUn configuration must be completed first.
Changing the PLL and Clock Frequency
1. Read the
CGU_STAT
• CGU_STAT.PLLEN =1 (enabled)
• CGU_STAT.PLOCK =1 (PLL is not locking)
• CGU_STAT.CLKSALGN =0 (clocks aligned)
2. Write the desired values into the CGU_DIV.CSEL, CGU_DIV.S0SEL, CGU_DIV.SYSSEL,
CGU_DIV.S1SEL, CGU_DIV.DSEL and CGU_DIV.OSEL bits with the CGU_DIV.UPDT bit cleared (=
0).
3. Write the desired values to the CGU_CTL.DF and CGU_CTL.MSEL bits.
4–6
CGU0
SYS_CLKIN0
CCLK0
CCLK1
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
CGU1
CCLK0
SYS_CLKIN1
CCLK1
SCLK0
SCLK1
DCLK
OCLK
CGU0
SYS_CLKIN0
CCLK0
CCLK1
SYSCLK
/2
SCLK0
SCLK1
DCLK
OCLK
CGU1
CCLK0
SYS_CLKIN1
CCLK1
SCLK0
SCLK1
DCLK
register. Verify that:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
OCLK8
OCLK9
/2
LINKPORT
MSI
CDU_CFG[n]
register must
Advertisement
Table of Contents
