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CDU Functional Description
This configuration provides the flexibility to meet the specific clock requirements of the different modules in the
system (core, DDR, or CAN module) without compromising the clocking of other modules. Such a flexibility is not
possible with a single CGU in the system. With two CGUs:
• Each CGU has its own set of clock multipliers and dividers, providing a greater number of orthogonal clocks
than possible with a single CGU.
• Each CGU can be clocked from a different CLKIN source, providing additional flexibility.
• CGU0 is always clocked by CLKIN0, whereas CGU1 can be clocked either by CLKIN0 or CLKIN1.
SYS_CLKIN0
SYS_CLKIN1
Black: mandatory settings
Red: optional settings
Figure 4-1: CGU/CDU Block Diagram
CDU Definitions
The Clock Descriptions table provides a brief description of the clocks supported by the processor.
Table 4-1: Clock Descriptions
Clock
CCLK0_0
CCLK1_0
SYSCLK_0
SCLK0_0
SCLK1_0
DCLK_0
OCLK_0
CCLK0_1
CCLK1_1
4–2
SYSCLK_0
SCLK1-0_0
CCLK1-0_0
SCLK1-0_0
CCLK1-0_0
DCLK_0
CGU0
OCLK_0
SCLK1-0_1
CCLK1-0_1
DCLK_1
OCLK_1
CGU1
Description
CCLK0 derived from CGU0
CCLK1 derived from CGU0
SYSCLK derived from CGU0
SCLK0 derived from CGU0
SCLK1 derived from CGU0
DCLK derived from CGU0
OCLK derived from CGU0
CCLK0 derived from CGU1
CCLK1 derived from CGU1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
System, L2 mem/cache, SEC, GIC,
high speed peripherals
Peripherals
CLKO2-0 (Cores)
Mux
CLKO9-3 (Peripherals)
CDU
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