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DMC Programming Model
driver impedance Rtt and ODT values to match the trace impedance. The connection reduces impedance disconti-
nuity and minimizes signal reflections.
The command has two variants named as ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). The
ZQCL command is issued during initialization and after self-refresh exit command. It can be issued later depending
on the system environment.
The DMC pads can be autocalibrated to the required driver impedance Rtt using an external resistance RZQ and
the On Die Termination (ODT) value using the corresponding bits (DMC_CAL_PADCTL2). The autocalibration
logic translates these values into a corresponding drive strength control inside the PHY and then routed to the
PADS. Autocalibration starts as soon as the DMC_CAL_PADCTL0.CALSTRT bit is programmed (set the DCLK
at the required frequency before setting this bit). Autocalibration expects the program to select two different mem-
ber sets of pads (address/command pads versus CLK/Data/DQS/DM pads).
On Die Termination (DDR2/DDR3)
The DMC supports dynamic On Die Termination (ODT) at the pads. When the controller ODT is set, the termi-
nation resistors in the pads are turned on when the controller reads data from the DRAM. These resistors are turned
off when the controller is writing to the DRAM. Controller ODT is enabled with the granularity of a byte lane. The
description of this feature can be obtained in the description of the corresponding PHY registers.
ODT resistance Rtt is selectable in the same way as DDR2 SDRAM ([A9, A6, A2] in MR1, [A10, A9] in MR2)
DDR3 SDRAM inherits the ODT function provided for DDR2 SDRAM, and provides extended ODT mode.
Synchronous ODT: ODT timing is the same as that of DDR2 SDRAM
Asynchronous ODT: ODT timing in the slow exit power-down mode
Dynamic ODT: Function that can dynamically switch the ODT resistance during a write operation without an
MRS command. It improves signal quality during a write operation.
Output Driver Impedance
Output driver impedance (Rtt) of DQ, DQS, /DQS/DM is selectable in the same way as DDR2 SDRAM ([A5,
A1] in MR1). Rtt can fluctuate with the process, voltage, and temperature (PVT). DDR2 SDRAM can calibrate Rtt
fluctuation due to PVT using the optional OCD (off-chip driver calibration) function. DDR3 SDRAM uses the
ZQ calibration function instead of the OCD function.
In addition to the driver impedance, the bidirectional pads (Data and DQS) also require the initialization sequence
to program the termination impedance by writing to the field DMC_CAL_PADCTL2.IMPRTT. The DMC pads
use parallel termination, one branch goes from the pad to the I/O supply. The other branch goes to the I/O ground.
The value programmed to this 8-bit field is the value to be used for each branch. There is a correction factor in-
volved while programming this register. The value of this correction factor is 0.8. For example, suppose that a termi-
nation of 50 Ω is required on the data pads to match with the board trace. The value is programmed to 100 × 0.8 =
80, as the two parallel paths lead to an effective impedance of 50 ohms.
10–18
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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