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Table 6-1: ADSP-SC58x RCU Register List (Continued)
Name
RCU_STAT
RCU_SVECT0
RCU_SVECT1
RCU_SVECT2
RCU_SVECT_LCK
ADSP-SC58x RCU Trigger List
Table 6-2: ADSP-SC58x RCU Trigger List Masters
Trigger ID
Name
Table 6-3: ADSP-SC58x RCU Trigger List Slaves
Trigger ID
Name
50
RCU0_SYSRST0
51
RCU0_SYSRST1
RCU Definitions
To make the best use of the RCU, it is useful to understand the terms in this section.
The target or source defines the following are types of resets.
Hardware Reset (by target)
All functional units except a small subsection of debug interfaces are set to their default states. State is lost in all non-
volatile storage.
System Reset (by target)
All functional units except the RCU, flash interface, and debug are set to their default states.
Core n Only Reset (by target)
Affects Core n only. The system software must guarantee that a bus master cannot access the core in reset state.
Hardware Reset (by source)
The SYS_HWRST input signal is asserted active (pulled low).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Status Register
Software Vector Register 0
Software Vector Register 1
Software Vector Register 2
SVECT Lock Register
Description
None
Description
RCU0 System Reset 0
RCU0 System Reset 1
RCU Functional Description
Sensitivity
Sensitivity
Pulse
Pulse
6–3
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