Analog Devices ADSP-SC58 Series Hardware Reference Manual page 432

Sharc+ processor
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ADSP-SC58x DMC Register Descriptions
Controller to PHY Interface Register
CPHY_CTL[15:0] (W)
Register given from Controller to PHY
CPHY_CTL[31:16] (W)
Register given from Controller to PHY
Figure 10-3: DMC_CPHY_CTL Register Diagram
Table 10-12: DMC_CPHY_CTL Register Fields
Bit No.
(Access)
31:0
CPHY_CTL
(RX/W)
10–26
15
14
0
31
30
0
Bit Name
Register given from Controller to PHY.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
0

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