ADSP-SC58x PORT Register Descriptions
Table 14-20: PORT_INEN_SET Register Fields (Continued)
Bit No.
(Access)
2
PX2
(R/W1S)
1
PX1
(R/W1S)
0
PX0
(R/W1S)
14–56
Bit Name
Port x Bit 2 Input Enable Set.
Port x Bit 1 Input Enable Set.
Port x Bit 0 Input Enable Set.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Effect
1 Set Bit. Set to enable the input driver.
0 No Effect
1 Set Bit. Set to enable the input driver.
0 No Effect
1 Set Bit. Set to enable the input driver.