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DMC Operating Modes
DDR2 Mode
This mode is the default mode of the DMC module and supports JESD79-2E compatible DDR2 SDRAM. In this
mode, the DMC_CTL.DDR3EN bit =0, the DMC_CTL.LPDDR bit =0, and the DMC_PHY_CTL4.DDRMODE bit
field is 0b'01.
DDR3 Mode
The DMC module supports JESD79-3E compatible double data rate DDR3 SDRAM. To configure this mode of
operation, first set (=1) the DMC_CTL.DDR3EN bit and set the DMC_PHY_CTL4.DDRMODE bit field to 0b'00.
LPDDR Mode
The DMC module supports JESD209A low-power DDR (LPDDR) SDRAM. To configure this mode of operation,
set (=1) the DMC_CTL.LPDDR bit and set the DMC_PHY_CTL4.DDRMODE bit field to 0b'11.
Deep Power-Down Mode
The DMC module supports JESD209A low-power DDR (LPDDR) SDRAM. To configure this mode of operation,
set (=1) the DMC_CTL.LPDDR bit and set the DMC_PHY_CTL4.DDRMODE bit field to 0b'11.
When the processor does not require the data stored in SDRAM (assume reset state of SDRAM), the DMC can put
the SDRAM in deep power-down mode. When the DMC is in deep power-down, any data accesses cause the DMC
to generate a bus error. To configure this mode, set (=1) the DMC_CTL.DPDREQ bit when low-power DMC opera-
tion is enabled (DMC_CTL.LPDDR =1).
The DMC_STAT.IDLE bit indicates the activity in the DMC. If this bit is set, there is no activity all through the
DMC. Deep power can be entered by setting the DMC_CTL.DPDREQ bit. The DMC_STAT.DPDACK bit is asser-
ted when the SDRAM enters deep power-down mode. The DMC stays in deep power-down mode as long as the
DMC_CTL.DPDREQ bit is asserted.
Clearing (=0) the DMC_CTL.DPDREQ bit causes the DMC to exit deep power-down mode. Also, when exiting
deep power-down mode, the controller clears the DMC_STAT.DPDACK bit. The user must re-initialize the DMC
after it comes out of deep power-down mode.
Self-Refresh Mode
For low-power consumption, the SDRAM can be put in self-refresh mode. When no data activity occurs, the DMC
can put the SDRAM in self refresh to save power. The DMC_STAT.IDLE bit indicates the activity on the DMC. If
this bit is set, there is no activity in the DMC.
Enable self-refresh mode by writing the DMC_CTL.SRREQ bit. The DMC stays in a self-refresh state as long as this
bit is asserted. The DMC_STAT.SRACK bit indicates when the SDRAM enters self-refresh mode.
When the DMC is in self-refresh mode, the DMC generates an SCB error when any data accesses (read or write
requests) is requested.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10–13
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