Analog Devices ADSP-SC58 Series Hardware Reference Manual page 936

PWM_AH
PWM_AH
Figure 19-7: Pulse Positioning Modes
Channel Low Side Output Dependent Operation Mode and Dead Time
The low-side output waveform can be programmed to depend on the waveform of the high-side output or to be
independent. The PWM uses the PWM_CHANCFG.MODELSC bit to control this functionality.
For example, channel A produces the high-side output PWM_AH and the low-side output PWM_AL. When the
PWM_CHANCFG.MODELSC bit =0, the low-side output is also generated using the high-side duty-cycle registers for
pulse width, the PWM_ACTL.PULSEMODEHI bits for pulse positioning and the PWM_CHANCFG.POLAH bit for
polarity. If the PWM_CH[x]_DT register is 0, the low-side output is an inverted version of the high-side output.
When the PWM_CH[x]_DT register is programmed with a non-zero value, both the high-side and low-side outputs
are scaled symmetrically about the points of transition in the zero dead time case. The PWM scales the output by
the value programmed in the PWM_CH[x]_DT register.
The Channel Outputs in Dependent Mode for Pulse Mode figures show the high and low-side outputs for the case
with zero and non-zero dead time for PWM_ACTL.PULSEMODEHI =00 and 01. DUTY0 is the value programmed
into the register. DUTY1 is the value programmed into the
PWM_AH0
PWM_CHANCFG.POLAH bit =1, indicates that both signals are active high. The
value DT.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Centre of Period
DUTY0
count
Assert for count < DUTY0
PULSEMODE = 00
DUTY 0
count
DUTY1
DUTY0 > DUTY1
Assert for
count <
DUTY0
De-Assert for
count <
DUTY1
PULSEMODE = 10
DUTY0
count
PWM_AH
Assert for count < DUTY0
De-assert for count > DUTY1
count
DUTY0 < DUTY1
PWM_AH
Channel Timing Control Unit
Centre of Period
DUTY1
De-assert for
count > DUTY1
PULSEMODE = 01
DUTY1
DUTY0
De- Assert for
count > DUTY1
Assert for count <
DUTY0
PULSEMODE = 11
register. The
PWM_AH1
PWM_CHA_DT register holds the
19–15