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LP Programming Model
6. Wait for the link port transmitter (connected externally) to be enabled with subsequent data transmission. The
application can wait for the receive service request interrupt to assert.
7. Clear the receive service request interrupt status by writing 1 to the LP_STAT.LRRQ bit.
8. Enable DMA by setting the DMA_CFG.EN bit.
9. Enable the link port by setting the LP_CTL.EN bit.
10. Wait for DMA to assert the transfer complete interrupt.
11. Clear the DMA interrupt source by writing 1 to the DMA_STAT.IRQDONE bit of the DMA status register.
Setting Up a Core Transmit Operation
This section describes the typical steps for using the link ports in processor core based transmission.
1. Enable the link port pins in the GPIO port mux using the appropriate
2. Install interrupt handlers for data transfer and for transfer status (service request interrupt). The interrupt han-
dlers for data transfer are the same source or ID as the DMA interrupt line in the SEC.
3. Configure the link port for transmission by setting the LP_CTL.TRAN bit) and enable the transmit request
interrupt mask by setting the LP_CTL.TRQMSK bit).
4. Program the link port clock divider by writing a value in to the
5. Wait for the link port receiver (connected externally) to be enabled. The application can wait for a transmit
service request interrupt to assert.
6. Clear the transmit service request interrupt status by writing 1 to the LP_STAT.LTRQ bit.
7. Enable the link port by setting the LP_CTL.EN bit.
8. The data request interrupt is asserted whenever there is free space in the FIFO. The application can write to the
LP_TX
register based on the FIFO conditions (half or empty) reflected in the LP_STAT.FFST bit field.
Setting Up a Core Receive Operation
This section describes the typical steps for using the link ports in processor core-based reception.
1. Enable the link port pins in the GPIO port mux using the appropriate
2. Install interrupt handlers for data transfer and for transfer status (service request interrupt). The interrupt han-
dlers for data transfer are the same source or ID as the DMA interrupt line in the SEC).
3. Configure link port for reception (clear LP_CTL.TRAN bit). Enable the receive request interrupt mask bit (set
LP_CTL.RRQMSK).
4. Wait for the link port transmit (connected externally) to be enabled with subsequent transmission of data. The
application can wait for receive service request interrupt to be asserted.
15–16
LP_DIV
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PORT_FER
and
PORT_MUX
register.
and
PORT_FER
PORT_MUX
registers.
registers.
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