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Efficiency Control Register
The
register control DMC features that improve throughput efficiency. These include features such
DMC_EFFCTL
as auto-refresh management, precharge options, and write data options.
PRECBANK7 (R/W)
Precharge Bank 7
PRECBANK6 (R/W)
Precharge Bank 6
PRECBANK5 (R/W)
Precharge Bank 5
PRECBANK4 (R/W)
Precharge Bank 4
IDLECYC (R/W)
Idle Cycle
Figure 10-9: DMC_EFFCTL Register Diagram
Table 10-18: DMC_EFFCTL Register Fields
Bit No.
(Access)
23:20
IDLECYC
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Idle Cycle.
The DMC_EFFCTL.IDLECYC bits select the number of cycles after which the DMC
issues any accumulated auto-refresh commands if postpone refresh is enabled
(DMC_CTL.PPREF =1). When DMC_EFFCTL.IDLECYC is set to 0, the DMC ig-
nores the DMC_CTL.PPREF selection and does not accumulate/postpone periodic
auto-refresh commands.
Note 1: By default, accumulated auto-refresh commands are issued after counting four
idle cycles.
Note 2: This value is ignored if DMC_CTL.PPREF is not set.
Note 3: Setting this value to 0000 overrides the "postpone refresh" feature and does
not accumulate/postpone periodic auto refreshes.
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
1
0
0
0
1
0
Description/Enumeration
0-15 0 to 15 Idle Cycles to Postpone Refresh Commands
ADSP-SC58x DMC Register Descriptions
0
0
PRECBANK0 (R/W)
Precharge Bank 0
PRECBANK1 (R/W)
Precharge Bank 1
PRECBANK2 (R/W)
Precharge Bank 2
PRECBANK3 (R/W)
Precharge Bank 3
16
0
NUMREF (R/W)
Number of Refresh Commands
10–35
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