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ADSP-SC58x TRU Register Descriptions
Slave Select Register
The TRU slave select registers (TRU_SSR[n]) each provide slave selection and register locking.
Figure 8-5: TRU_SSR[n] Register Diagram
Table 8-9: TRU_SSR[n] Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
7:0
SSR
(R/W)
8–20
15
14
13
0
0
0
SSR (R/W)
SSRn Slave Select
31
30
29
0
0
0
LOCK (R/W)
SSRn Lock
Bit Name
SSRn Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
TRU_SSR[n].LOCK bit is enabled, the
SSRn Slave Select.
The
TRU_SSR[n]
sponds. For example, when a
ID n, a trigger that is generated by trigger master ID n results in a trigger out to the
slave.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock register
1 Lock register
register selects the trigger master ID to which the trigger slave re-
TRU_SSR[n]
0 No master specified
1-139 Range of valid masters
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
TRU_SSR[n]
register is read only.
register is set to respond to trigger master
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