Analog Devices ADSP-SC58 Series Hardware Reference Manual page 895

ADSP-SC58x EPPI Register Descriptions
Table 18-49: EPPI_CTL Register Fields
Bit No.
(Access)
31 CLKGATEN
(R/W)
30 MUXSEL
(R/W)
29 DMAFINEN
(R/W)
28 DMACFG
(R/W)
27 RGBFMTEN
(R/W)
18–56
Bit Name
Clock Gating Enable.
The EPPI_CTL.CLKGATEN bit enables using the EPPI_FS3 pin as a clock gating
pin. When EPPI_CTL.CLKGATEN is set, the EPPI_FS3 pin acts as a clock gating
signal, and both the internal and external clock are gated. Note that the EPPI_FS3
pin gating signal is active low, and the EPPI_CTL.CLKGATEN selection is ignored if
EPPI_CTL.MUXSEL is set or EPPI_CTL.FSCFG equals 0x3.
MUX Select.
The EPPI_CTL.MUXSEL bit enables multiplexing of a primary and alternate camera
using the EPPI main data and clock lines. For more information on this feature, see
the EPPI functional description.
DMA Finish Enable.
The EPPI_CTL.DMAFINEN bit selects whether or not the EPPI sends a finish com-
mand (010) through the DDE COMMAND line soon after a frame/line is received
completely.
One or Two DMA Channels Mode.
The EPPI_CTL.DMACFG bit is valid only if EPPI_CTL.SPLTEO is set. If
EPPI_CTL.DMACFG is set, the EPPI uses two DMA channels. And, if
EPPI_CTL.DMACFG is cleared, the EPPI uses only one DMA channel.
RGB Formatting Enable.
For 16- or 18-bit transmit modes only, the EPPI_CTL.RGBFMTEN bit enables con-
version of RGB888 from memory into RGB666 output data (18-bit transmit) or ena-
bles conversion of RGB888 from memory into RGB565 output data (16-bit transmit).
Note that EPPI_CTL.SPLTEO and EPPI_CTL.RGBFMTEN should never be set
simultaneously.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable
1 Enable
0 Normal Operation
1 Multiplexed Operation
0 No Finish Command
1 Enable Send Finish Command
0 PPI Uses One DMA Channel
1 PPI Uses Two DMA Channels
0 Disable RGB Formatted Output
1 Enable RGB Formatted Output