Analog Devices ADSP-SC58 Series Hardware Reference Manual page 79

Half SPORT 'A' Divisor Register .......................................................................................................... 34–77
Half SPORT 'B' Divisor Register .......................................................................................................... 34–78
Half SPORT 'A' Error Register ............................................................................................................. 34–79
Half SPORT 'B' Error Register ............................................................................................................. 34–81
Half SPORT 'A' Multichannel Control Register ................................................................................... 34–83
Half SPORT 'B' Multichannel Control Register ................................................................................... 34–85
Half SPORT 'A' Multichannel Status Register ...................................................................................... 34–87
Half SPORT 'B' Multichannel Status Register ...................................................................................... 34–88
Half SPORT 'A' Rx Buffer (Primary) Register ...................................................................................... 34–89
Half SPORT 'B' Rx Buffer (Primary) Register ...................................................................................... 34–90
Half SPORT 'A' Rx Buffer (Secondary) Register ................................................................................... 34–91
Half SPORT 'B' Rx Buffer (Secondary) Register ................................................................................... 34–92
Half SPORT 'A' Tx Buffer (Primary) Register ...................................................................................... 34–93
Half SPORT 'B' Tx Buffer (Primary) Register ...................................................................................... 34–94
Half SPORT 'A' Tx Buffer (Secondary) Register ................................................................................... 34–95
Half SPORT 'B' Tx Buffer (Secondary) Register ................................................................................... 34–96
Precision Clock Generators (PCG)
Features........................................................................................................................................................ 35–1
Functional Description ................................................................................................................................ 35–1
ADSP-SC58x PCG Register List .............................................................................................................. 35–2
Internal Interface ...................................................................................................................................... 35–2
Serial Clock .............................................................................................................................................. 35–3
Frame Sync ............................................................................................................................................... 35–3
Frame Sync Output ............................................................................................................................... 35–3
Divider Mode Selection......................................................................................................................... 35–3
Phase Shift ............................................................................................................................................ 35–4
Pulse Width .......................................................................................................................................... 35–5
Default Pulse Width.............................................................................................................................. 35–5
Input Clock Source Considerations ....................................................................................................... 35–5
Timing Example for I
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
2
S Mode .............................................................................................................. 35–6
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