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Figure 19-21: Duty Cycle Notation for Heightened-Precision Edge Placement
In the normal modes of operation (not involving heightened-precision edge placement), only the
value is programmed. The duty value programmed is a two's complement integer value. If a value of -1 is desired,
the
register is programmed with the number 0xFFFF (which is the two's complement of 1 in 16 bits).
PWM_AH0
In the heightened-precision mode, if a duty value corresponding to 0.75 is required, the equivalent two's comple-
ment value of 0.75 in the Q15.8 format is computed: 1111_1111_1111_1111.0100_0000 = 0xFFFF.40. In this
case, the
register is programmed to 0xFFFF and the
PWM_AH0
Heightened-Precision Edge Placement Example
The following is an example of heightened precision edge placement.
On the positive side of the fractional of the duty cycle, at 2 t
PWM_AH0_HP
registers are calculated as follows.
The
=0x0002 and
PWM_AH0
The
PWM_AH_DUTY0
[15:14] represent the decimal part or heightened-precision value and bits [31:16] represent the coarse duty cycle.
The value for the combined registers is
On the negative side of the fractional of the duty cycle, at –2 t
registers are calculated as follows:
PWM_AH0_HP
The coarse register represents the next count of the coarse value for negative values so that –2 becomes –3. These
values are the two's complement of the positive offset (value = 3)
(bits 7:6).
To derive the correct format for a negative duty-cycle value, for example, –2.25, use: coarse value + 1 =3 for the
coarse value and 1 for 0.25. Write out the absolute value as a 32-bit number first:
0000 0000 0000 0011 (.) 0100 0000 0000 0000
Then take the two's complement of the entire 32-bit number:
1111 1111 1111 1101 (.) 1100 0000 0000 0000
NOTE:
This value is also written into the full duty register (PWM_AH_DUTY0). The correct value for the com-
bined registers written in the
The above examples only consider 2 bits of precision, while the ADSP-CM41xF supports up to 4 bits.
NOTE:
That means bits [7:4] of the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
s
14
13
12
11
10
=0x40 (bits 7:6).
PWM_AH0_HP
register contains the bit fields from both the
PWM_AH_DUTY0
PWM_AH_DUTY0
PWM_AH_DUTY0
PWM_AH0
PWM_AH0_HP
9
8
7
6
5
4
3
2
1
0
-1 -2 -3 -4 -5 -6 -7 -8
PWM_AH0_HP
+ 0.25 t
CK
CK
PWM_AH0
=0x00024000.
– 0.25 t
CK
PWM_AH0
register is 0xFFFDC000.
register can be used to define the higher precision. Bits
register is programmed to 0x40.
, the values for the
PWM_AH0
and
PWM_AH0_HP
, the values for the
PWM_AH0
CK
= 0xFFFD and
PWM_AH0_HP
Operating Modes
PWM_AH0
register
and
registers. Bits
and
=0xC0
19–29
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