Table of Contents
Advertisement
NOTE:
If another transmission is pending (in the
queued until after all pending operations have finished and all stop bits are transmitted.
The transmission of break command/inter-frame gap precedes transmission of the number of stop bits as set in the
UART_CTL.STB and UART_CTL.STBH bit fields.
The UART receiver can detect break commands through the break indicator (UART_STAT.BI) flag. This flag re-
ports that an entire UART frame has been received in low state. It does not report whether the duration of the re-
ceived low pulse was exact or at least 13 bit-times as LIN masters transmit. Typically, the break indicator meets LIN
requirements. The processor can use GP timers to determine the pulse width more precisely, if necessary.
Each UART_RX pin is also routed to a GP timer through its alternate capture input (TACI). This functionality is
not only useful for bit rate detection (autobaud) but also helps to measure the pulse widths precisely on the
UART_RX input. Additionally, the GP timers can issue an interrupt request or a fault condition when the received
pulse width is shorter than a bit time or longer than the worst-case break condition. The windowed watchdog width
mode of the GP timers controls this functionality.
UART Mode Receive Operation (Core)
The receive operation uses the same data format as the transmit configuration except that one valid stop bit is always
sufficient. The UART_CTL.STB and UART_CTL.STBH bits have no impact on the receiver.
The UART receiver senses the falling edges of the receive input. When it detects an edge, the receiver starts sampling
the input according to settings in the
close to its midpoint. If sampled low, it assumes a valid start condition. Otherwise, it discards the detected falling
edge.
After detection of the start bit, the received word is shifted into the
After the corresponding stop bit is received, the content of the
ceive FIFO and is accessible by reading the
The receive FIFOs and the
received before software reads the
UART_RBR
register and the receive FIFO from being overwritten by further data until the software clears the
UART_STAT.OE bit. However, the data in the
run occurs.
The sampling clock is 16 times faster than the bit clock. The receiver oversamples every bit 16 times and makes a
majority-decision based on the middle three samples. This functionality improves immunity against noise and haz-
ards on the line. The receiver disregards spurious pulses of less than two times the sampling clock period.
Normally, the receiver samples every incoming bit at exactly the 7th, 8th and 9th sample clock. If, however, the
UART_CLK.EDBO bit is set to 1, the receiver samples bits roughly at 7/16th, 8/16th, and 9/16th of their period.
This configuration achieves better bit rate granularity and accuracy as required at high operation speeds. Hardware
design must ensure that the incoming signal is stable between 6/16th and 10/16th of the nominal bit period.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_CLK
register. The receiver samples the start bit (majority sampling)
UART_RBR
UART_RBR
register act as a 9-stage receive buffer. If the stop bit of the ninth word is
register, an overrun error is reported. Overruns protect data in the
UART_RBR
UART_RSR
UART_TSR
register), the
UART_RSR
UART_RSR
register.
register is immediately destroyed as soon as the over-
UART Data Transfer Modes
UART_TAIP
initiated pulse is
register.
register is transferred to the 8-deep re-
17–13
Advertisement
Table of Contents
