Analog Devices ADSP-SC58 Series Hardware Reference Manual page 103

Sources .................................................................................................................................................. 51–19
Window Complete .............................................................................................................................. 51–19
All Channels Complete ....................................................................................................................... 51–20
MAC Status ........................................................................................................................................ 51–20
Service .................................................................................................................................................... 51–20
Effect Latency ............................................................................................................................................ 51–21
Write Effect Latency ............................................................................................................................... 51–21
FIR Throughput ........................................................................................................................................ 51–21
ADSP-SC58x FIR Register Descriptions .................................................................................................. 51–21
FIR Chain Pointer Register ................................................................................................................... 51–23
FIR Coefficient Count Register ............................................................................................................. 51–24
FIR Coefficient Index Register .............................................................................................................. 51–25
FIR Coefficient Modifier Register ......................................................................................................... 51–26
FIR Global Control Register .................................................................................................................. 51–27
FIR Channel Control Register ............................................................................................................... 51–29
Debug Address Register ......................................................................................................................... 51–30
FIR Debug Control Register .................................................................................................................. 51–31
FIR Debug Data Read Register ............................................................................................................. 51–32
FIR Debug Data Write Register ............................................................................................................. 51–33
FIR DMA Status Register ...................................................................................................................... 51–34
FIR Input Data Base Register ................................................................................................................ 51–36
FIR Input Data Count Register ............................................................................................................. 51–37
FIR Input Data Index Register .............................................................................................................. 51–38
FIR Input Data Modifier Register ......................................................................................................... 51–39
FIR MAC Status Register ...................................................................................................................... 51–40
FIR Output Data Base Register ............................................................................................................. 51–43
FIR Output Data Count Register .......................................................................................................... 51–44
FIR Output Data Index Register ........................................................................................................... 51–45
FIR Output Data Modifier Register ...................................................................................................... 51–46
IIR Accelerator (IIR)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference ciii