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The byte enable pins are both three-stated during all asynchronous reads and are driven low during 16-bit asynchro-
nous writes. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 =0 and
SMC_ABE0 =1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1 =1 and
SMC_ABE0 =0.
NOTE:
Some SRAM devices expect byte-enable signals to be driven low during read accesses rather than being
three-stated, which can be achieved using external pull-down resistors. For applications requiring alternate
functions on the byte-enable pins during run time where pull-down resistors are not an option, the same
functionality can be achieved using the external logic shown as follows:
Figure 11-1: External Logic
Avoiding Bus Contention
Bus contention occurs when one device is getting off the bus and another is getting on. If the first device is slow to
three-state and the second device is quick to drive, the devices contend. Bus contention causes excessive power dissi-
pation and can lead to device failure.
There are two cases where contention can occur.
• When a read followed by a write to the same memory space occurs, there is a potential for bus contention. The
data bus drivers used for the write can potentially contend with the drivers used by the memory device being
read.
• When there are back-to-back reads from two different memory spaces, the two memory devices addressed by
the two reads can contend at the transition between the two read operations.
To avoid contention, program the turnaround time appropriately in the extended time registers
SMC_B3ETIM). The programming is done by setting the number of clock cycles between these types of accesses on
a bank-by-bank basis.
The idle time bit (SMC_B0ETIM.IT) applies to similar back-to-back access types on the same bank. The transi-
tion time bit (SMC_B0ETIM.TT) applies to the SMC_B0ETIM.IT bit. For actual turnaround situations, idle
time and transition time function in an accumulated fashion. The sequence of access types and times are:
• A write followed by write to same bank – SMC_B0ETIM.IT
• A read followed by read to same bank – SMC_B0ETIM.IT
• A write followed by read to same bank – SMC_B0ETIM.IT + SMC_B0ETIM.TT
• A read followed by write to same bank – SMC_B0ETIM.IT + SMC_B0ETIM.TT
• Any access to a given bank followed by any access to a different bank – SMC_B0ETIM.IT +
SMC_B0ETIM.TT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMC0_ABE0
SMC0_AOE
SMC0_ABE1
SRAM_BLE
SMC0_AOE
SMC Architectural Concepts
SRAM_BHE
(SMC_B0ETIM
–
11–5
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