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ADSP-SC58x SMPU Register Descriptions
Region n Control Register
The
SMPU_RCTL[n]
region is controlled and defined by this register and the SMPU_RADDR[n], SMPU_RIDA[n], SMPU_RIDB[n],
SMPU_RIDMSKA[n], and
WIDCINV (R/W)
Write Transaction ID Compare Invert
WPROTEN (R/W)
Write Transaction Protection Enable
RIDCINV (R/W)
Read Transaction ID Compare Invert
Figure 13-10: SMPU_RCTL[n] Register Diagram
Table 13-14: SMPU_RCTL[n] Register Fields
Bit No.
(Access)
11
WIDCINV
(R/W)
10
WPROTEN
(R/W)
9
RIDCINV
(R/W)
13–24
register is used to define the level of protection for a region of memory. The protection of a
SMPU_RIDMSKB[n]
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Write Transaction ID Compare Invert.
The SMPU_RCTL[n].WIDCINV bit inverts the write ID match result.
Write Transaction Protection Enable.
The SMPU_RCTL[n].WPROTEN bit enables protection against ID-based write
transactions for the memory region.
Read Transaction ID Compare Invert.
When the SMPU_RCTL[n].RIDCINV bit is set, the read ID match result is invert-
ed.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers.
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 Write transaction ID comparison result not inverted
1 Write transaction ID comparison result inverted
0 Write transaction ID-based protection disabled
1 Write transaction ID-based protection enabled
0 Read transaction ID comparison result not inverted
1 Read transaction ID comparison result inverted
0
0
EN (R/W)
Region Enable
SIZE (R/W)
Memory Region Size
RPROTEN (R/W)
Read Transaction Protection Enable
16
0
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