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Blackfin ADSP-BF537
Analog Devices Blackfin ADSP-BF537 Manuals
Manuals and User Guides for Analog Devices Blackfin ADSP-BF537. We have
3
Analog Devices Blackfin ADSP-BF537 manuals available for free PDF download: Hardware Reference Manual, Service Manual, Specification
Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual (1218 pages)
Brand:
Analog Devices
| Category:
Computer Hardware
| Size: 4 MB
Table of Contents
Table of Contents
3
Preface
43
Intended Audience
43
Purpose of this Manual
43
Manual Contents
44
Technical or Customer Support
47
What's New in this Manual
47
Supported Processors
48
Product Information
49
Myanalog.com
49
Processor Product Information
49
Related Documents
50
Online Technical Documentation
51
Accessing Documentation from Visualdsp
52
Accessing Documentation from Windows
52
Accessing Documentation from the Web
53
Printed Manuals
53
Visualdsp++ Documentation Set
53
Data Sheets
54
Hardware Tools Manuals
54
Processor Manuals
54
Conventions
55
Register Diagram Conventions
56
Introduction
59
Peripherals
59
Memory Architecture
62
Internal Memory
64
External Memory
64
I/O Memory Space
65
DMA Support
65
External Bus Interface Unit
67
PC133 SDRAM Controller
67
Asynchronous Controller
67
Ports
68
General-Purpose I/O (GPIO)
68
Two-Wire Interface
69
Controller Area Network
70
Ethernet MAC
72
Parallel Peripheral Interface
72
SPORT Controllers
74
Serial Peripheral Interface (SPI) Port
76
Timers
76
UART Ports
77
Real-Time Clock
78
Watchdog Timer
79
Clock Signals
80
Dynamic Power Management
81
Full on Mode (Maximum Performance)
81
Active Mode (Moderate Power Savings)
81
Sleep Mode (High Power Savings)
81
Deep Sleep Mode (Maximum Power Savings)
82
Hibernate State
82
Voltage Regulation
82
Boot Modes
83
Instruction Set Description
85
Development Tools
87
Chip Bus Hierarchy
91
Overview
91
Interface Overview
93
Internal Clocks
94
Core Bus Overview
94
Peripheral Access Bus (PAB)
96
PAB Agents (Masters, Slaves)
96
PAB Arbitration
96
PAB Performance
97
DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB)
98
DAB Arbitration
98
DAB Bus Agents (Masters)
99
DAB, DCB, and DEB Performance
100
External Access Bus (EAB)
100
Arbitration of the External Bus
101
DEB/EAB Performance
101
Memory
103
Memory Architecture
103
L1 Data SRAM
104
L1 Data Cache
110
Boot ROM
110
External Memory
110
Processor-Specific Mmrs
110
DMEM_CONTROL Register
111
DTEST_COMMAND Register
112
System Interrupts
113
Overview
113
Features
113
Interfaces
114
Description of Operation
114
Events and Sequencing
114
System Peripheral Interrupts
119
Programming Model
126
System Interrupt Initialization
126
System Interrupt Processing Summary
126
System Interrupt Controller Registers
128
Sic_Iarx Registers
130
SIC_IMASK Register
132
SIC_ISR Register
133
SIC_IWR Register
134
Programming Examples
135
Clearing Interrupt Requests
135
Direct Memory Access
139
Overview and Features
139
DMA Controller Overview
143
External Interfaces
144
Internal Interfaces
144
Peripheral DMA
145
Memory DMA
147
Handshaked Memory DMA Mode
149
Modes of Operation
150
Register-Based DMA Operation
150
Stop Mode
151
Autobuffer Mode
152
Two-Dimensional DMA Operation
152
Examples of Two-Dimensional DMA
153
Descriptor-Based DMA Operation
154
Descriptor List Mode
155
Descriptor Array Mode
156
Variable Descriptor Size
156
Mixing Flow Modes
157
Functional Description
158
DMA Operation Flow
158
DMA Startup
158
DMA Refresh
163
Work Unit Transitions
165
DMA Transmit and MDMA Source
166
DMA Receive
168
Stopping DMA Transfers
169
DMA Errors (Aborts)
170
DMA Control Commands
172
Restrictions
176
Transmit Restart or Finish
176
Receive Restart or Finish
177
Handshaked Memory DMA Operation
178
Pipelining DMA Requests
179
HMDMA Interrupts
181
DMA Performance
182
DMA Throughput
183
Memory DMA Timing Details
186
Static Channel Prioritization
186
Temporary DMA Urgency
188
Memory DMA Priority and Scheduling
189
Traffic Control
191
Programming Model
193
Synchronization of Software and DMA
194
Continuous Transfers Using Autobuffering
196
Single-Buffer DMA Transfers
196
Descriptor Structures
198
Descriptor Queue Management
199
Descriptor Queue Using Interrupts on Every Descriptor
200
Descriptor Queue Using Minimal Interrupts
201
Software Triggered Descriptor Fetches
203
DMA Registers
205
DMA Channel Registers
206
Dmax_Peripheral_Map
209
Dmax_Config/Mdma_Yy_Config Registers
212
Mdma_Yy_Irq_Status Registers
216
Mdma_Yy_Start_Addr Registers
220
Dmax_Curr_Addr/Mdma_Yy_Curr_Addr Registers
221
Dmax_X_Count/Mdma_Yy_X_Count Registers
223
Dmax_Curr_X_Count Mdma_Yy_Curr_X_Count Registers
224
Dmax_X_Modify Mdma_Yy_X_Modify Registers
226
Mdma_Yy_Y_Count Registers
228
Dmax_Curr_Y_Count Mdma_Yy_Curr_Y_Count Registers
229
Dmax_Y_Modify/Mdma_Yy_Y_Modify Registers
231
Dmax_Next_Desc_Ptr Mdma_Yy_Next_Desc_Ptr Registers
232
Dmax_Curr_Desc_Ptr Mdma_Yy_Curr_Desc_Ptr Registers
234
HMDMA Registers
236
Hmdmax_Control Registers
237
Hmdmax_Bcinit Registers
239
Hmdmax_Ecount Registers
240
Hmdmax_Ecinit Registers
241
Hmdmax_Ecurgent Registers
242
DMA Traffic Control Registers
243
DMA_TC_CNT Register
244
Register-Based 2D Memory DMA
245
Initializing Descriptors in Memory
249
Software-Triggered Descriptor Fetch Example
252
Handshaked Memory DMA Example
254
External Bus Interface Unit
257
EBIU Overview
257
Block Diagram
260
Internal Memory Interfaces
261
Shared Pins
262
Registers
262
System Clock
263
Error Detection
263
Bus Request and Grant
264
Operation
264
AMC Overview and Features
265
Features
265
Asynchronous Memory Interface
265
Asynchronous Memory Address Decode
266
AMC Pin Description
266
AMC Description of Operation
267
Avoiding Bus Contention
267
External Access Extension
268
AMC Functional Description
268
Programmable Timing Characteristics
268
Asynchronous Reads
269
Asynchronous Writes
270
Adding External Access Extension
272
Byte Enables
274
AMC Registers
277
AMC Programming Examples
280
SDC Overview and Features
281
SDRAM Configurations Supported
282
SDRAM External Bank Size
283
Internal SDRAM Bank Select
285
SDC Interface Overview
286
SDRAM Performance
287
SDC Description of Operation
288
Row Precharge
289
Burst Type
290
Bank Activate Command
291
Exit Self-Refresh Mode
292
Trcd
293
Trfc
294
Tref
295
SDC Address Muxing
298
Multibank Operation
299
Core and DMA Arbitration
300
Changing Power Management During Runtime
302
SDC Commands
303
Mode Register Set Command
305
Bank Activation Command
307
Single Precharge Command
308
Self-Refresh Mode
309
Self-Refresh Exit Command
310
SDC SA10 Pin
311
SDC Configuration
312
Example SDRAM System Block Diagrams
314
SDC Register Definitions
316
EBIU_SDBCTL Register
318
Using Sdrams with Systems Smaller than 16M Byte
321
EBIU_SDGCTL Register
323
EBIU_SDSTAT Register
334
SDC Programming Examples
335
Overview
341
Interface Overview
342
Description of Operation
345
Functional Description
346
ITU-R 656 Input Modes
350
Active Video Only
351
ITU-R 656 Output Mode
352
General-Purpose PPI Modes
353
Data Input (RX) Modes
355
No Frame Syncs
356
Or 3 Internal Frame Syncs
357
Data Output (TX) Modes
358
Or 3 Internal Frame Syncs
359
Frame Synchronization in GP Modes
360
Modes with External Frame Syncs
361
Programming Model
363
PPI Registers
366
PPI_STATUS Register
370
PPI_DELAY Register
374
PPI_FRAME Register
375
Programming Examples
376
Data Transfer Scenarios
379
Overview
381
Interface Overview
382
External Interface
384
Pins
385
Internal Interface
386
Power Management
387
Operation
390
Receive DMA Operation
391
Frame Reception and Filtering
393
RX Automatic Pad Stripping
397
RX DMA Data Alignment
398
RX Frame Status Buffer
399
RX Frame Status Classification
400
RX IP Frame Checksum Calculation
401
RX DMA Direction Errors
402
Transmit DMA Operation
404
Flexible Descriptor Structure
407
Late Collisions
408
TX Frame Status Classification
409
TX DMA Direction Errors
410
Power Management
411
Ethernet Operation in the Sleep State
413
Magic Packet Detection
414
Remote Wake-Up Filters
415
Ethernet Event Interrupts
418
RX/TX Frame Status Interrupt Operation
422
Startup and Shutdown
423
Programming Model
426
Multiplexing Scheme
427
Configure MAC Registers
428
Configure PHY
430
Receiving Data
431
Control-Status Register Group
443
EMAC_OPMODE Register
444
EMAC_ADDRLO Register
450
EMAC_ADDRHI Register
451
EMAC_HASHLO and EMAC_HASHHI Registers
452
EMAC_STAADD Register
456
EMAC_STADAT Register
458
EMAC_VLAN1 and EMAC_VLAN2 Registers
460
EMAC_WKUP_CTL Register
461
EMAC_WKUP_FFMSK2, and EMAC_WKUP_FFMSK3 Registers
464
EMAC_WKUP_FFCMD Register
469
EMAC_WKUP_FFOFF Register
471
EMAC_WKUP_FFCRC0 and EMAC_WKUP_FFCRC1 Registers
472
System Interface Register Group
473
EMAC_SYSTAT Register
475
Ethernet MAC Frame Status Registers
477
EMAC_RX_STKY Register
483
EMAC_RX_IRQE Register
487
EMAC_TX_STAT Register
488
EMAC_TX_STKY Register
492
EMAC_TX_IRQE Register
494
EMAC_MMC_RIRQS Register
495
EMAC_MMC_RIRQE Register
497
EMAC_MMC_TIRQS Register
499
EMAC_MMC_TIRQE Register
501
MAC Management Counter Registers
503
EMAC_MMC_CTL Register
504
Programming Examples
505
Ethernet Structures
506
MAC Address Setup
509
PHY Control Routines
510
Overview
513
Interface Overview
514
CAN Mailbox Area
516
CAN Mailbox Control
518
CAN Protocol Basics
519
CAN Operation
521
Transmit Operation
524
Retransmission
525
Single Shot Transmission
527
Data Acceptance Filter
530
Remote Frame Handling
531
Time Stamps
532
Temporarily Disabling Mailboxes
533
Functional Operation
534
CAN Interrupts
535
Global Interrupt
536
Event Counter
538
CAN Warnings and Errors
540
Error Frames
541
Error Levels
543
Debug and Test Modes
545
Low Power Features
549
CAN Built-In Sleep Mode
550
Register Definitions
551
Global Registers
554
CAN_CONTROL Register
555
CAN_STATUS Register
556
CAN_DEBUG Register
557
CAN_TIMING Register
558
CAN_GIM Register
559
CAN_GIF Register
560
Can_Amxx Registers
561
Can_Mbxx_Id1 Registers
565
Can_Mbxx_Id0 Registers
567
Can_Mbxx_Timestamp Registers
569
Can_Mbxx_Length Registers
571
Can_Mbxx_Datax Registers
573
Mailbox Control Registers
580
Can_Mcx Registers
581
Can_Mdx Registers
582
Can_Rmpx Register
583
Can_Rmlx Register
584
Can_Opssx Register
585
Can_Trsx Registers
586
Can_Trrx Registers
587
Can_Aax Register
588
Can_Tax Register
589
CAN_MBTD Register
590
Can_Mbimx Registers
591
Can_Mbtifx Registers
592
Can_Mbrifx Registers
593
Universal Counter Registers
594
CAN_UCCNF Register
595
CAN_UCCNT Register
596
Error Registers
597
CAN_EWR Register
598
Programming Examples
599
Initializing and Enabling CAN Mailboxes
601
Initiating CAN Transfers and Processing Interrupts
602
Overview
607
Interface Overview
609
External Interface
610
Master out Slave in (MOSI)
611
Serial Peripheral Interface Slave Select Input Signal
612
Enable Output Signals
613
Slave Select Inputs
616
Internal Interfaces
618
SPI Transmit Data Buffer
619
SPI Receive Data Buffer
620
SPI General Operation
623
SPI Control
624
Clock Signals
625
SPI Baud Rate
626
Mode Fault Error (MODF)
627
Transmission Error (TXE)
628
Interrupt Output
629
Master Mode Operation
630
Transfer Initiation from Master (Transfer Modes)
631
Slave Mode Operation
632
Slave Ready for a Transfer
633
Programming Model
634
Master Mode DMA Operation
636
Slave Mode DMA Operation
638
SPI Registers
646
Programming Examples
651
Starting a Transfer
652
Post Transfer and Next Transfer
653
Stopping
654
DMA Initialization Sequence
655
SPI Initialization Sequence
656
Starting a Transfer
657
Overview
661
Interface Overview
662
External Interface
663
Serial Data Signal (SDA)
664
Internal Interfaces
665
Description of Operation
666
Bus Arbitration
667
Start and Stop Conditions
668
General Call Support
669
Fast Mode
670
Clock Signal
671
Error Signals and Flags
672
TWI Slave Status
675
TWI FIFO Status
676
TWI Interrupt Status
677
Functional Description
680
Master Mode Clock Setup
682
Master Mode Receive
683
Repeated Start Condition
684
Receive/Transmit Repeated Start Sequence
686
Programming Model
688
Register Descriptions
690
TWI_SLAVE_CTL Register
691
TWI_SLAVE_ADDR Register
693
TWI_MASTER_CTL Register
694
TWI_MASTER_ADDR Register
697
TWI_MASTER_STAT Register
698
TWI_FIFO_STAT Register
700
TWI_INT_STAT Register
703
TWI_XMT_DATA16 Register
704
TWI_RCV_DATA8 Register
705
TWI_RCV_DATA16 Register
706
Programming Examples
707
Slave Mode Setup
712
Electrical Specifications
719
Overview
721
Features
722
Interface Overview
723
SPORT Pin/Line Terminations
729
Description of Operation
730
Setting SPORT Modes
731
Stereo Serial Operation
732
Multichannel Operation
735
Multichannel Enable
738
Frame Syncs in Multichannel Mode
739
The Multichannel Frame
740
Multichannel Frame Delay
741
Window Offset
742
Channel Selection Register
743
Multichannel DMA Data Packing
744
Support for H.100 Standard Protocol
745
X Clock Recovery Control
746
Maximum Clock Rate Restrictions
748
Companding
749
Clock Signal Options
750
Framed Versus Unframed
751
Internal Versus External Frame Syncs
752
Active Low Versus Active High Frame Syncs
753
Data Independent Transmit Frame Sync
757
Moving Data between Sports and Memory
758
PAB Errors
759
SPORT Registers
765
Register Writes and Effective Latency
767
Sportx_Rcr1 and Sportx_Rcr2 Registers
772
Data Word Formats
777
Sportx_Tx Register
778
Sportx_Rx Register
780
Sportx_Stat Register
783
Sportx_Tclkdiv and Sportx_Rclkdiv Registers
784
Sportx_Tfsdiv and Sportx_Rfsdiv Register
785
Sportx_Mcmcn Registers
786
Sportx_Chnl Register
787
Sportx_Mrcsn Registers
788
Sportx_Mtcsn Registers
790
Programming Examples
792
SPORT Initialization Sequence
793
DMA Initialization Sequence
795
Interrupt Servicing
797
Starting a Transfer
798
Advertisement
Analog Devices Blackfin ADSP-BF537 Service Manual (628 pages)
VisualDSP++ 5.0 Device Drivers and System for Blackfin Processors
Brand:
Analog Devices
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
3
Device Drivers and System Services
1
Copyright Information
2
Introduction
3
Table of Contents
22
Preface
31
Purpose of this Manual
31
Intended Audience
31
Manual Contents Description
32
Technical or Customer Support
34
Supported Processors
34
Product Information
35
Analog Devices Web Site
35
Myanalog.com
35
Notation Conventions
37
Introduction
39
System Services Overview
40
General
41
Application Interface
45
Dependencies
46
Initialization
48
Termination
48
System Services Directory and File Structure
49
Accessing the System Services API
49
Linking in the System Services Library
51
Rebuilding the System Services Library
53
Dual-Core Considerations
54
Examples
54
RTOS Considerations
55
Interoperability of System Services with VDK
55
Deployment of Services Within a Multi-Threaded Application
56
Device Driver Overview
57
Application Interface
58
Device Driver Architecture
59
Initialization
61
Interaction with System Services
61
Device Driver Directory and File Structure
62
Termination
62
Accessing the Device Driver API
63
Device Driver File Locations
65
Linking in the Device Driver Library
66
Rebuilding the Device Driver Library
67
Examples on Distribution
68
Interrupt Manager
69
Introduction
70
Interrupt Manager Initialization
72
Interrupt Manager Termination
73
Core Event Controller Functions
74
Adi_Int_Cechook() Function
74
Adi_Int_Cecunhook() Function
76
Interrupt Handlers
76
System Interrupt Controller Functions
77
Adi_Int_Sicdisable
78
Adi_Int_Sicenable
78
Adi_Int_Sicgetivg
78
Adi_Int_Sicinterruptasserted
78
Adi_Int_Sicsetivg
79
Adi_Int_Sicwakeup
79
Protecting Critical Code Regions
80
Modifying IMASK
82
Examples
83
File Structure
84
Interrupt Manager API Reference
85
Notation Conventions
85
Adi_Int_Init
86
Adi_Int_Terminate
87
Adi_Int_Cechook
88
Adi_Int_Cecunhook
90
Adi_Int_Clearimaskbits
92
Adi_Int_Entercriticalregion
94
Adi_Int_Exitcriticalregion
96
Adi_Int_Sicdisable
97
Adi_Int_Sicenable
98
Adi_Int_Sicgetivg
99
Adi_Int_Sicinterruptasserted
100
Adi_Int_Sicsetivg
101
Adi_Int_Setimaskbits
102
Adi_Int_Sicwakeup
104
Power Management Module
105
Getting Started
105
Introduction
106
PM Module Operation - Getting Started
107
Dual-Core Considerations
109
Using Automatic Synchronization
109
Synchronization Requirement
110
Running Applications on One Core Only
111
Running Applications on both Cores
112
Built-In Lock Variable and Linking Considerations
114
Synchronization between Cores
114
SDRAM Initialization Prior to Loading an Executable
117
Initialization
117
Sdram Initialization Prior to Loading an Executable
118
Power Management API Reference
119
Notation Conventions
119
Adi_Pwr_Adjustfreq
120
Adi_Pwr_Control
122
Adi_Pwr_Getconfigsize
124
Adi_Pwr_Getfreq
125
Adi_Pwr_Getpowermode
126
Adi_Pwr_Getpowersaving
127
Adi_Pwr_Init
129
Adi_Pwr_Loadconfig
134
Adi_Pwr_Reset
135
Adi_Pwr_Saveconfig
136
Adi_Pwr_Setfreq
137
Adi_Pwr_Setmaxfreqforvolt
139
Adi_Pwr_Setpowermode
140
Adi_Pwr_Setvoltageregulator
142
Public Data Types and Enumerations
146
Adi_Pwr_Command
146
Adi_Pwr_Command_Pair
151
Adi_Pwr_Csel
151
Adi_Pwr_Df
152
Adi_Pwr_Input_Delay
152
Adi_Pwr_Output_Delay
152
Adi_Pwr_Mode
153
Adi_Pwr_Package_Kind
153
Adi_Pwr_Pcc133_Compliance
154
Adi_Pwr_Proc_Kind
154
Adi_Pwr_Result
154
Adi_Pwr_Ssel
156
Adi_Pwr_Vddext
157
Adi_Pwr_Vlev
157
Adi_Pwr_Vr_Canwe
158
Adi_Pwr_Vr_Ckelow
158
Adi_Pwr_Vr_Usbwe
158
Adi_Pwr_Vr_Clkbufoe
159
Adi_Pwr_Vr_Freq
159
Adi_Pwr_Vr_Gain
159
Adi_Pwr_Vr_Phywe
160
Adi_Pwr_Vr_Wake
160
PM Module Macros
160
External Bus Interface Unit Module
165
Introduction
166
Using the EBIU Module
167
EBIU API Reference
174
Notation Conventions
174
Adi_Ebiu_Adjustsdram
175
Adi_Ebiu_Control
176
Adi_Ebiu_Getconfigsize
179
Adi_Ebiu_Init
180
Adi_Ebiu_Loadconfig
186
Adi_Ebiu_Saveconfig
187
Public Data Types and Enumerations
188
Adi_Ebiu_Result
188
Adi_Ebiu_Sdram_Bank_Value
191
Adi_Ebiu_Time
191
Adi_Ebiu_Timing_Value
192
Adi_Ebiu_Asynch_Bank_Timing
193
Adi_Ebiu_Asynch_Bank_Value
194
Setting Control Values in the EBIU Module
195
Adi_Ebiu_Command
195
Adi_Ebiu_Command_Pair
202
Adi_Ebiu_Sdram_Enable
202
Command Value Enumerations
202
Adi_Ebiu_Sdram_Bank_Col_Width
203
Adi_Ebiu_Sdram_Bank_Size
203
Adi_Ebiu_Sdram_Module_Type
203
Adi_Ebiu_Cmd_Set_Sdram_Sctle
204
Adi_Ebiu_Sdram_Emren
204
Adi_Ebiu_Sdram_Pasr
205
Adi_Ebiu_Sdram_Srfs
205
Adi_Ebiu_Sdram_Tcsr
205
Adi_Ebiu_Sdram_Ebufe
206
Adi_Ebiu_Sdram_Pupsd
206
Adi_Ebiu_Sdram_Fbbrw
207
Adi_Ebiu_Sdram_Psm
207
Adi_Ebiu_Bank_Number
208
Adi_Ebiu_Sdram_Cddbg
208
Adi_Ebiu_Asynch_Bank_Data_Path
209
Adi_Ebiu_Asynch_Bank_Enable
209
Adi_Ebiu_Asynch_Clkout
209
Adi_Ebiu_Asynch_Bank_Ardy_Enable
210
Adi_Ebiu_Asynch_Bank_Ardy_Polarity
210
Adi_Ebiu_Asynch_Hold_Time
210
Adi_Ebiu_Asynch_Setup_Time
211
Adi_Ebiu_Asynch_Transition_Time
211
Deferred Callback Manager
213
Introduction
213
Using the Deferred Callback Manager
215
Interoperability with an RTOS
220
Adi_Dcb_Forward
220
Adi_Dcb_Registerisr
223
Handling Critical Regions Within Callbacks
223
DCB Manager API Reference
224
Notation Conventions
224
Adi_Dcb_Close
225
Adi_Dcb_Control
226
Adi_Dcb_Init
229
Adi_Dcb_Open
231
Adi_Dcb_Post
233
Adi_Dcb_Remove
235
Adi_Dcb_Terminate
236
Public Data Types and Macros
237
Adi_Dcb_Callback_Fn
237
Adi_Dcb_Command_Pair
237
Adi_Dcb_Command
238
Adi_Dcb_Entry_Hdr
238
Adi_Dcb_Result
239
Dma Manager
241
Introduction
242
Theory of Operation
243
Overview
243
DMA Manager Initialization
244
DMA Manager Termination
245
Memory DMA and Peripheral DMA
246
Controlling Memory Streams
247
Opening Memory Streams
247
Memory Transfers
248
One-Dimensional Transfers (Linear Transfers)
248
Two-Dimensional Transfers
249
Closing Memory Streams
250
Controlling DMA Channels
250
Opening DMA Channels
251
Circular Transfers
252
Large Descriptor Chaining Model
252
Single Transfers
252
Small Descriptor Chaining Model
252
Arrays of Descriptors
260
Configuring a DMA Channel
260
Closing a DMA Channel
261
Transfer Completions
261
Callbacks
262
Memory Stream Callbacks
262
Polling
262
Circular Transfer Callbacks
263
Descriptor Callbacks
263
Descriptor-Based Sub-Modes
264
Loopback Sub-Mode
264
Streaming Sub-Mode
265
DMA Channel to Peripheral Mapping
266
Interrupts
267
Sensing a Mapping
267
Setting a Mapping
267
Hooking Interrupts
268
Unhooking Interrupts
268
Two-Dimensional DMA
269
DMA Traffic Control
271
DMA Manager API Reference
272
Notation Conventions
272
Adi_Dma_Buffer
274
Adi_Dma_Close
276
Adi_Dma_Control
277
Adi_Dma_Getmapping
279
Adi_Dma_Init
280
Adi_Dma_Memoryclose
281
Adi_Dma_Memorycopy
282
Adi_Dma_Memorycopy2D
284
Adi_Dma_Memoryopen
286
Adi_Dma_Open
288
Adi_Dma_Queue
290
Adi_Dma_Setmapping
291
Adi_Dma_Terminate
292
Public Data Structures, Enumerations, and Macros
293
Adi_Dma_Channel_Handle
294
ADI_DMA_DESCRIPTOR_UNION and ADI_DMA
294
Data Types
294
Descriptor_Handle
294
Adi_Dma_2D_Transfer
295
Adi_Dma_Stream_Handle
295
Data Structures
295
Adi_Dma_Config_Reg
296
Adi_Dma_Descriptor_Array
296
Adi_Dma_Descriptor_Large
296
Adi_Dma_Descriptor_Small
297
Adi_Dma_Tc_Set
297
Adi_Dma_Channel_Id
298
Adi_Dma_Event
298
Adi_Dma_Tc_Get
298
General Enumerations
298
Adi_Dma_Mode
299
Adi_Dma_Pmap
300
Adi_Dma_Result
300
Adi_Dma_Stream_Id
300
ADI_DMA_CONFIG_REG Field Values
301
Adi_Dma_Di_En
301
Adi_Dma_Di_Sel
301
Adi_Dma_Dma2D
301
Adi_Dma_Tc_Parameter
301
Adi_Dma_En
302
Adi_Dma_Wdsize
302
Adi_Dma_Wnr
302
DMA Commands
302
Programmable Flag Service
305
Introduction
306
Operation
307
Initialization
307
Flag Ids
308
Termination
308
Adi_Flag_Close
309
Adi_Flag_Open
309
Adi_Flag_Set
309
Adi_Flag_Setdirection
309
Flag Control Functions
309
Adi_Flag_Clear
310
Adi_Flag_Sense
310
Adi_Flag_Toggle
310
Callbacks
310
Adi_Flag_Installcallback
311
Adi_Flag_Removecallback
312
Adi_Flag_Resumecallbacks
313
Adi_Flag_Settrigger
313
Adi_Flag_Suspendcallbacks
313
Coding Example
313
Initialization
314
Controlling an Output Flag
315
Opening a Flag
315
Setting Flag Direction
315
Installing a Callback Function
316
Sensing the Value of a Flag
316
Removing Callbacks
317
Suspending and Resuming Callbacks
317
Termination
318
Flag Service API Reference
319
Notation Conventions
319
Adi_Flag_Clear
320
Adi_Flag_Close
321
Adi_Flag_Init
322
Adi_Flag_Open
324
Adi_Flag_Setdirection
325
Adi_Flag_Terminate
326
Adi_Flag_Set
327
Adi_Flag_Toggle
328
Adi_Flag_Sense
329
Adi_Flag_Installcallback
330
Adi_Flag_Removecallback
332
Adi_Flag_Suspendcallbacks
333
Adi_Flag_Resumecallbacks
334
Adi_Flag_Suspendcallbacks
334
Adi_Flag_Settrigger
335
Public Data Types, Enumerations, and Macros
336
Adi_Flag_Id
336
Adi_Flag_Result
337
Associated Macros
337
Adi_Flag_Event
338
Adi_Flag_Direction
339
Adi_Flag_Trigger
339
Timer Service
341
Introduction
342
Operation
343
Initialization
343
Termination
343
Adi_Tmr_Close
344
Adi_Tmr_Open
344
Basic Timer Functions
344
Timer Ids
344
Adi_Tmr_Gpcontrol
345
Adi_Tmr_Gpgroupenable
345
Adi_Tmr_Reset
345
General-Purpose Timer Functions
345
Adi_Tmr_Corecontrol
346
Adi_Tmr_Watchdogcontrol
346
Core Timer Functions
346
Watchdog Timer Functions
346
Adi_Tmr_Getperipheralid
347
Callbacks
347
Peripheral Timer Functions
347
Adi_Tmr_Installcallback
348
Adi_Tmr_Removecallback
349
Coding Example
349
Configuring a Timer
350
Opening a Timer
350
Enabling and Disabling Timers
352
Installing a Callback Function
353
Removing Callbacks
354
Notation Conventions
355
Timer Service API Reference
355
Adi_Tmr_Init
356
Adi_Tmr_Open
357
Adi_Tmr_Terminate
358
Adi_Tmr_Close
359
Adi_Tmr_Reset
360
Adi_Tmr_Corecontrol
361
Adi_Tmr_Watchdogcontrol
362
Adi_Tmr_Gpcontrol
363
Adi_Tmr_Gpgroupenable
364
Adi_Tmr_Installcallback
366
Adi_Tmr_Removecallback
368
Adi_Tmr_Getperipheralid
369
Public Data Types, Enumerations, and Macros
370
Timer Ids
370
Associated Macros
371
Adi_Tmr_Result
372
Adi_Tmr_Core_Cmd
373
Adi_Tmr_Event
373
Adi_Tmr_Wdog_Cmd
374
Adi_Tmr_Gp_Cmd
375
Introduction
380
Using the Port Control Manager
381
Notation Conventions
383
Port Control Manager API Reference
383
Adi_Ports_Init
384
Adi_Ports_Terminate
385
Adi_Ports_Enableppi
386
Adi_Ports_Enablespi
387
Adi_Ports_Enablesport
388
Adi_Ports_Enableuart
389
Adi_Ports_Enablecan
390
Adi_Ports_Enabletimer
391
Adi_Ports_Enablegpio
393
Adi_Ports_Result
394
Public Data Types, Enumerations, and Macros
394
Directive Enumeration Values
395
Device Driver Model Overview
401
Device Manager Overview
404
Using the Device Manager
404
Data
405
Theory of Operation
405
Initializing the Device Manager
406
Device Manager Termination
407
Opening a Device
408
Configuring a Device
409
Dataflow Method
410
Enabling Dataflow
413
Providing Buffers to a Device
413
Closing a Device
414
Callbacks
414
Initialization Sequence
415
Stackable Drivers
415
Chained with Loopback
416
Chained Without Loopback
416
Circular
416
Deciding on a Dataflow Method
416
Creating One-Dimensional Buffers
417
Sequential with and Without Loopback
417
Creating Two-Dimensional Buffers
421
Creating Circular Buffers
424
Creating Sequential One-Dimensional Buffers
426
Device Manager API Description
428
Device Manager Design
428
Dataflow Enumerations
429
Handles
429
Memory Usage Macros
429
Callback Events
430
Command Ids
430
Return Codes
430
Buffer Data Types
431
Circular Buffer Callback Options
431
API Function Definitions
432
Physical Driver Entry Point
432
Device Manager Code
432
Data Structures
432
Static Data
432
Adi_Dev_Init Functional Description
433
API Functional Description
433
Static Function Declarations
433
Adi_Dev_Close Functional Description
434
Adi_Dev_Open Functional Description
434
Adi_Dev_Read Functional Description
435
Adi_Dev_Control Functional Description
436
Adi_Dev_Write Functional Description
436
Pddcallback
439
Static Functions
439
Dmacallback
440
Preparebufferlist
441
Setdataflow
442
Physical Driver Design
443
Physical Driver Design Overview
443
Physical Device Driver API Description
445
Extensible Definitions
446
Physical Driver Include File ("XXX.h)
446
Adi_Dev_Pdd_Entry_Point
448
Adi_Pdd_Open Functional Description
449
Adi_Pdd_Control Functional Description
450
Adi_Pdd_Read Functional Description
451
Adi_Pdd_Write Functional Description
453
Adi_Pdd_Close Functional Description
454
Device Manager API Reference
455
Notation Conventions
455
Adi_Dev_Close
456
Adi_Dev_Control
457
Adi_Dev_Init
458
Adi_Dev_Open
459
Adi_Dev_Read
461
Adi_Dev_Terminate
462
Adi_Dev_Write
463
Adi_Dev_Buffer_Type
464
Device Manager Public Data Types and Enumerations
464
Adi_Dev_Direction
465
Adi_Dev_Mode
465
Callback Events
466
Result Codes
467
COMMAND Ids
470
Adi_Dev_1D_Buffer
473
Adi_Dev_2D_Buffer
474
Adi_Dev_Circular_Buffer
475
Adi_Dev_Buffer_Pair
476
Adi_Dev_Seq_1D_Buffer
476
Adi_Dev_Dma_Access
477
Adi_Dev_Dma_Info
477
Adi_Dev_Access_Register
478
Adi_Dev_Frequencies
478
Adi_Dev_Access_Register_Block
479
Adi_Dev_Access_Register_Field
479
Adi_Dev_Buffer
480
Notation Conventions
481
Physical Driver API Reference
481
Adi_Pdd_Close
482
Adi_Pdd_Control
483
Adi_Pdd_Open
484
Adi_Pdd_Read
486
Adi_Pdd_Write
487
Examples
488
Introduction
489
Initialization
490
Operation
490
Termination
491
Setting and Reading the Date and Time
492
One Second Periodic Event
493
Real-Time Clock Events
493
Daily Periodic Event
494
Hourly Periodic Event
494
One Minute Periodic Event
494
Each Day Alarm Event
495
Once Only Alarm Event
495
Periodic or One-Shot Stopwatch Event
495
Callbacks
496
Pending Writes Complete Event
496
Installing a Callback
497
The Callback List
497
Removing a Callback
498
The Real-Time Clock Service Interrupt Handler
498
Using the Clienthandle Parameter in a Callback
498
Coding Example
499
Notation and Naming Conventions
504
RTC Service Application Programming Interface (API)
504
RTC Service API Functions
505
Adi_Rtc_Init()
506
Adi_Rtc_Terminate()
507
Adi_Rtc_Setdatetime()
508
Adi_ Rtc_Getdatetime
509
Adi_Rtc_Installcallback()
510
Adi_Rtc_Removecallback()
512
Adi_Rtc_Enablewakeup()
513
Adi_Rtc_Disablewakeup()
514
Adi_Rtc_Resetstopwatch()
515
Real-Time Clock Service API Data Types and Enumerations
516
Tm Structure
516
Event Ids
517
Result Codes
518
Deferred Callback Service
519
Interdependencies
519
Interrupt Manager Service
519
System Service Requirements
521
Interrupt Manager Service
528
Deferred Callback Service
529
DMA Service
530
Semaphore Service
530
Device Manager
531
Real-Time Clock Service
531
Advanced Configuration
532
Custom Configuration of Device Drivers
532
Dynamic Memory Usage
532
Dynamic Memory Usage
534
File Cache
537
File System Service API Reference
538
Notation and Naming Conventions
538
Adi_Fss_Init
540
Adi_Fss_Terminate
543
Adi_Fss_Control
544
Adi_Fss_Fileopen
550
Adi_Fss_Fileclose
552
Adi_Fss_Filewrite
553
Adi_Fss_Fileread
554
Adi_Fss_Fileseek
555
Adi_Fss_Filetell
557
Adi_Fss_Iseof
558
Adi_Fss_Fileremove
559
Adi_Fss_Filerename
560
Adi_Fss_Diropen
561
Adi_Fss_Dirclose
562
Adi_Fss_Dirread
563
Adi_Fss_Dirseek
564
Adi_Fss_Dirtell
565
Adi_Fss_Dirrewind
566
Adi_Fss_Dirchange
567
Adi_Fss_Getcurrentdir
568
Adi_Fss_Dircreate
569
Adi_Fss_Dirremove
570
Adi_Fss_File_Handle
571
Adi_Fss_Volume_Ident
571
Adi_Fss_Wchar
571
File System Service API Data Types and Enumerations
571
Adi_Fss_Cmd_Value_Pair
572
Adi_Fss_Dir_Handle
572
Adi_Fss_Device_Def
573
Adi_Fss_Dir_Entry
573
Result Codes
575
The Standard C I/O Interface Functions
577
Fopen
578
Fclose
579
Fwrite
580
Fread
581
Fprintf
582
Fscanf
583
Fgetc
584
Fgets
585
Fputc
586
Fputs
587
Fseek
588
Ftell
589
Feof
590
Additional POSIX Functions Supported by the FSS
591
Opendir
592
Closedir
593
Readdir
594
Readdir_R
595
Rewinddir
596
Seekdir
597
Telldir
598
Mkdir
599
Rmdir
600
Rename
601
Remove
602
Extensibility
603
Description
604
Harddiskaccess
604
Configuration
605
Harddiskformat
605
Configuration
606
Description
606
Analog Devices Blackfin ADSP-BF537 Specification (2 pages)
EZ-KIT Lite for Analog Devices Blackfin Processor
Brand:
Analog Devices
| Category:
Computer Hardware
| Size: 0 MB
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