Analog Devices ADSP-SC58 Series Hardware Reference Manual page 384

ADSP-SC58x L2CTL Register Descriptions
Control Register
The register includes a write protection bit, enables L2 banks, and selects mapping of banks (as ECC
L2CTL_CTL
RAM or data RAM).
ECCMAP7 (R/W)
ECC Map Bank 7
ECCMAP6 (R/W)
ECC Map Bank 6
ECCMAP5 (R/W)
ECC Map Bank 5
ECCMAP4 (R/W)
ECC Map Bank 4
ECCMAP3 (R/W)
ECC Map Bank 3
ECCMAP2 (R/W)
ECC Map Bank 2
ECCMAP1 (R/W)
ECC Map Bank 1
ECCMAP0 (R/W)
ECC Map Bank 0
LOCK (R/W)
Lock
Figure 9-5: L2CTL_CTL Register Diagram
Table 9-6: L2CTL_CTL Register Fields
Bit No.
(Access)
31 LOCK
(R/W)
16 DISURP
(R/W)
9–12
15 14 13 12 11 10 9
0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the L2CTL_CTL.LOCK
bit is set, the
Disable Urgent Request Priority.
The L2CTL_CTL.DISURP disables urgent request priority mode for all L2 banks.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
register is read only (locked).
L2CTL_CTL
0 Unlock
1 Lock
0 Enable URP
1 Disable URP
0
0
BK0EDIS (R/W)
Bank 0 ECC Disable
BK1EDIS (R/W)
Bank 1 ECC Disable
BK2EDIS (R/W)
Bank 2 ECC Disable
BK3EDIS (R/W)
Bank 3 ECC Disable
BK4EDIS (R/W)
Bank 4 ECC Disable
BK5EDIS (R/W)
Bank 5 ECC Disable
BK6EDIS (R/W)
Bank 6 ECC Disable
BK7EDIS (R/W)
Bank 7 ECC Disable
0
DISURP (R/W)
Disable Urgent Request Priority