Analog Devices ADSP-SC58 Series Hardware Reference Manual page 786

ADSP-SC58x SPI Register Descriptions
Table 16-37: SPI_TXCTL Register Fields (Continued)
Bit No.
(Access)
13:12 TRWM
(R/W)
8 TDU
(R/W)
6:4 TDR
(R/W)
3 TWCEN
(R/W)
16–80
Bit Name
FIFO Regular Watermark.
The SPI_TXCTL.TRWM bits select the transmit FIFO (SPI_TFIFO) watermark
level for regular data bus requests. When an urgent
bled with SPI_TXCTL.TUWM, the SPI_TXCTL.TRWM selection is used as the
deassertion condition for any SPI_ILAT.TUWM interrupt requests that are latched.
Transmit Data Underrun.
The SPI_TXCTL.TDU bit selects handling for transmit data requests when the trans-
mit buffer (SPI_TFIFO) is empty. If enabled and
transmits zero as data. If disabled and
last word in the buffer as data.
Transmit Data Request.
The SPI_TXCTL.TDR bits select transmit FIFO (SPI_TFIFO) watermark condi-
tions that direct the SPI to generate a transmit status interrupt request.
Transmit Word Counter Enable.
The SPI_TXCTL.TWCEN bit enables the decrement of the transmit word count
(SPI_TWC) register when the count is not zero and SPI_TXCTL.TTI is enabled.
Enabling SPI_TXCTL.TWCEN prevents transmit underrun errors from occurring.
The SPI_TXCTL.TWCEN bit is valid only when the SPI is a master.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
SPI_TFIFO
0 Full TFIFO
1 TFIFO less than 25% empty
2 TFIFO less than 50% empty
3 TFIFO less than 75% empty
SPI_TFIFO
SPI_TFIFO is empty, the SPI transmits the
0 Send last word when SPI_TFIFO is empty
1 Send zeros when SPI_TFIFO is empty
0 Disabled
1 Not full TFIFO
2 25% empty TFIFO
3 50% empty TFIFO
4 75% empty TFIFO
5 Empty TFIFO
0 Disable
1 Enable
watermark is ena-
is empty, the SPI