Analog Devices ADSP-SC58 Series Hardware Reference Manual page 446

ADSP-SC58x DMC Register Descriptions
Table 10-19: DMC_EMR1 Register Fields (Continued)
Bit No.
(Access)
5:3 AL
(R/W)
2 RTT0
(R/W)
1 DIC
(R/W)
0 DLLEN
(R/W)
10–40
Bit Name
Additive Latency.
The DMC_EMR1.AL bits select a number of added latency time for CAS operations
in terms of clock cycles (t
sheet for the SDRAM being used in your system.
Termination Resistance 0.
The DMC_EMR1.RTT0 bit and the DMC_EMR1.RTT1 bits select the SDRAM ter-
mination resistance.
RTT1=0, RTT0=0: No ODT at memory device
RTT1=0, RTT0=1: 75 Ohm ODT at memory device
RTT1=1, RTT0=0: 150 Ohm ODT at memory device
RTT1=1, RTT0=1: 50 Ohm ODT at memory device
For more information about this operation, see the data sheet for the SDRAM being
used in your system.
Output Driver Impedance Control.
The DMC_EMR1.DIC bit selects the drive strength mode for the SDRAM. For more
information about this operation, see the data sheet for the SDRAM being used in
your system. It must be kept at 0 if the SDRAM does not support this bit.
DLL Enable.
The DMC_EMR1.DLLEN bit enables the DLL in the SDRAM. For more information
about this operation, see the data sheet for the SDRAM being used in your system.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
). For more information about this operation, see the data
CK
0 0 Clock Cycles Added
1 1 Clock Cycle Added
2 2 Clock Cycles Added
3 3 Clock Cycles Added
4 4 Clock Cycles Added
5 5 Clock Cycles Added
0 Full Strength
1 Reduced Strength
0 Enable DLL (Normal Operation)
1 Disable DLL (Test/Debug Operation)