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L2 System Memory Architectural Concepts
Table 9-4: Fixed Priority With Priority Elevation
Channel
L2 Refresh Request
Port 0 Read Channel Urgent Request
Port 0 Write Channel Urgent Request
Port 1 Read Channel Urgent Request
Port 1 Write Channel Urgent Request
Port 0 Read Channel Normal Request
Port 0 Write Channel Normal Request
Port 1 Read Channel Normal Request
Port 1 Write Channel Normal Request
Data Integrity
The following sections provide information on how the L2 system memory ensures data integrity.
ECC Algorithm
Hsaio encoding calculates the ECC syndrome. A 7-bit syndrome is generated during write operation and stored as a
7-bit parity field along with the 32 data bits. Each data bit contributes to three parity bits according. Each parity bit
represents the XOR value of 13 or 14 data bits according to the following mapping:
9–6
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Priority Level
9 (highest)
8
7
6
5
4
3
2
1 (lowest)
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