Analog Devices ADSP-SC58 Series Hardware Reference Manual page 185

ADSP-SC58x CGU Register Descriptions
Table 3-19: CGU_STAT Register Fields (Continued)
Bit No.
(Access)
20 WDIVERR
(R/W1C)
19 WDFMSERR
(R/W1C)
17 LWERR
(R/W1C)
16 ADDRERR
(R/W1C)
15 OSCWDSTATF
(R/NW)
14:12 OSCWDSTATFC
(R/NW)
3–34
Bit Name
Write to DIV Error.
The CGU_STAT.WDIVERR bit indicates a write access to the
trigger an alignment sequence or to change the CGU_DIV.CSEL,
CGU_DIV.SYSSEL, CGU_DIV.S0SEL, CGU_DIV.S1SEL, or
CGU_DIV.DSEL bit values) while the PLL is locked, but still aligning the clocks.
Read after write accesses to the
value even if the clock frequency change is still in progress.
Write to DF or MSEL Error.
The CGU_STAT.WDFMSERR bit indicates a write access to the
change the CGU_CTL.DF or CGU_CTL.MSEL bit values while the PLL is locking.
Lock Write Error.
The CGU_STAT.LWERR bit indicates an attempt to write to write-protected (locked)
CGU registers. The CGU issues a bus error for this condition.
Address Error.
The CGU_STAT.ADDRERR bit indicates an attempt to make a read or write access to
unimplemented addresses or accesses are non-aligned. The CGU issues a bus error for
this condition.
Oscillator Watchdog Status Fault.
The CGU_STAT.OSCWDSTATF bit indicates a fault in the oscillator watchdog
(CGU's OSC_WDSTAT[1:0]) input pins.
Oscillator Watchdog Status Fault Code.
The CGU_STAT.OSCWDSTATFC bit field indicates the nature of the fault in the os-
cillator watchdog (CGU's OSC_WDSTAT[1:0]) input pins.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
and
CGU_STAT CGU_DIV
0 No Error
1 Write DIV Error
0 No Error
1 Write DF/MSEL Error
0 No Error
1 Lock Write Error
0 No Error
1 Address Error
0 No Fault
1 Fault
0 No Fault
1 No Input Clock
CGU_DIV register (to
registers return the new
CGU_CTL register to