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Core Reset Outputs Control Register
The RCU core reset control n registers (RCU_CRCTL) include a lock bit (RCU_CRCTL.LOCK) and a core reset bit
(RCU_CRCTL.CR[n]) for each core reset signal on the product.
Figure 6-2: RCU_CRCTL Register Diagram
Table 6-7: RCU_CRCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
2:0
CR[n]
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
CR[n] (R/W)
Core Reset Outputs
31
30
29
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the RCU_CRCTL.LOCK
bit is set, the
Core Reset Outputs.
The RCU_CRCTL.CR[n] bits control CRES[1:0] core reset signals. The
RCU_CRES[n] signals can be individually controlled. They are reset to their default
value by a hard reset or a system reset. For each RCU_CRES[n], the selected
RCU0_CRMSKi[n] bit is cleared.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
register is read only (locked).
RCU_CRCTL
0 Unlock
1 Lock
0 RCU_CRES[2:0] Deasserted
7 RCU_CRES[2:0] Asserted
ADSP-SC58x RCU Register Descriptions
4
3
2
1
0
0
0
1
1
0
20
19
18
17
16
0
0
0
0
0
6–11
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