Analog Devices ADSP-SC58 Series Hardware Reference Manual page 745

Table 16-19: SPI_CTL Register Fields (Continued)
Bit No.
(Access)
21:20 MIOM
(R/W)
18 FMODE
(R/W)
17:16 FCWM
(R/W)
15 FCPL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Multiple I/O Mode (Only on SPI2).
The SPI_CTL.MIOM bits enable SPI operation in dual I/O mode (DIOM) or quad
I/O mode (QIOM).
These bits can only be changed when the SPI is disabled (SPI_CTL.EN =0).
Fast-Mode Enable.
The SPI_CTL.FMODE bit enables fast mode operation for SPI receive transfers. SPI
transmit operations in fast mode are the same as normal mode.
Flow Control Watermark.
The SPI_CTL.FCWM bits select the watermark level of the transmit channel
(SPI_TFIFO
trol operation. These bits are applicable only when the SPI is a slave
(SPI_CTL.MSTR = 0) and flow control is enabled (SPI_CTL.FCEN =1). When
the watermark condition is met, the SPI slave deasserts the SPI_RDY pin.
Flow Control Polarity.
The SPI_CTL.FCPL bit selects flow control polarity for the SPI_RDY pin when
flow control is enabled. When the SPI_RDY pin is active, the SPI is indicating it is
ready for data transfer.
Description/Enumeration
0 No MIOM (disabled)
1 DIOM operation
2 QIOM operation (Only on SPI2)
3 Reserved
0 Disable
1 Enable
buffer) or receive channel (SPI_RFIFO
0 TFIFO empty or RFIFO full
1 TFIFO 75% or more empty, or RFIFO 75% or more
full
2 TFIFO 50% or more empty, or RFIFO 50% or more
full
3 Reserved
0 Active-low RDY
1 Active-high RDY
ADSP-SC58x SPI Register Descriptions
buffer) that triggers flow con-
16–39