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ADSP-SC58x SPI Register Descriptions
Receive FIFO Data Register
The
register has an interface to the receive shift register in the SPI and has an interface to the process-
SPI_RFIFO
or's data buses. The top level of the buffer is visible to programs as the 32-bit
(number of word locations) of the receive FIFO is actually flexible with transfer word size. The size of the receive
FIFO is 8 if the word size is 8-bit, or the size is 4 if the word size is 16-bit, or the size is 2 if the word size is 32-bit.
Both masters and slaves may stop or stall receive transfers based on FIFO status. When the receive FIFO is full, the
SPI master stops initiating new transfers on the SPI if SPI_RXCTL.RTI is enabled. A slave may stall the SPI
interface when the content of the FIFO crosses the selected watermark. If data reception continues after
SPI_RFIFO
is full, the data in the receive FIFO is invalid. The SPI indicates this condition with receive overrun
(SPI_STAT.ROR) error. This condition is possible when SPI_RXCTL.RTI =0 and SPI_RXCTL.REN =1 for a
master, or for a slave that does not exercise flow control.
Note that the receive FIFO is reset (cleared) when the SPI is disabled after being enabled.
Figure 16-30: SPI_RFIFO Register Diagram
Table 16-28: SPI_RFIFO Register Fields
Bit No.
(Access)
31:0
DATA
(R/NW)
16–62
15
14
0
0
DATA[15:0] (R)
Receive FIFO Data
31
30
0
0
DATA[31:16] (R)
Receive FIFO Data
Bit Name
Receive FIFO Data.
The SPI_RFIFO.DATA bit field contains the FIFO receive data.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
SPI_RFIFO
register, but the size
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
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