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• To change the PLL frequency while all cores are idle, set the CGU_CTL.WFI bit (=1).
• To change the PLL frequency while the cores are active, clear the CGU_CTL.WFI bit (=0).
4. Read the
CGU_STAT
• CGU_STAT.PLLEN = 1 (enabled)
• CGU_STAT.PLOCK = 1 (not locking)
• CGU_STAT.CLKSALGN = 0 (clocks aligned)
5. If clocks switch from CGUm clocks to CGUn input clocks, read the
CGU_CCBF_STAT
clock buffers, respectively. The CGU_SCBF_STAT[3:0] bit field corresponds to the OUTCLK, DCLK,
SCLK1, and SCLK0 clock buffers, respectively.
6. Read the
CDU_STAT
CLKOn configuration change in progress).
7. Write to the
CDU_CLKINSEL
8. Write to the CDU_CFG[n].SEL bit to select the clock source (the CDU_CFG[n].EN bit should =1.)
9. Read the
CDU_CFG[n]
10. Verify that the CDU_STAT.CLKO0 through CDU_STAT.CLKO9 bits =0.
CLKOn is reconfigured.
Changing the Clock Frequency
Use the following procedure to change a clock frequency.
1. Read the
CGU_STAT
2. Write the desired values into the CGU_DIV.CSEL, CGU_DIV.S0SEL, CGU_DIV.SYSSEL,
CGU_DIV.S1SEL, CGU_DIV.DSEL and CGU_DIV.OSEL bits with the CGU_DIV.UPDT bit =1.
3. Read the
CGU_DIV
CGU_DIV.S1SEL, CGU_DIV.DSEL and CGU_DIV.OSEL bit values are correct.
4. Read the
CGU_STAT
5. If clocks switch from CGUm clocks to CGUn input clocks, read the
CGU_CCBF_STAT
clock buffers, respectively. The CGU_SCBF_STAT[3:0] bit field corresponds to the OUTCLK, DCLK,
SCLK1, and SCLK0 clock buffers, respectively.
6. Read the
CDU_STAT
CLKOn configuration change in progress).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register. Verify that:
registers. The CGU_CCBF_STAT[1:0] bit field corresponds to the CCLK1 and CCLK0
register. Verify that the CDU_STAT.CLKO0 through CDU_STAT.CLKO9 bits =0 (no
register to select the CGU's CLKIN input clock.
register. Verify that the
register to verify that the CGU_STAT.CLKSALGN bit =0 (clocks aligned).
registers to verify that the CGU_DIV.CSEL, CGU_DIV.S0SEL, CGU_DIV.SYSSEL,
register to verify that the CGU_STAT.CLKSALGN =0 (clocks aligned).
registers. The CGU_CCBF_STAT[1:0] bit field corresponds to the CCLK1 and CCLK0
register. Verify that the CDU_STAT.CLKO5 through CDU_STAT.CLKO9 bits =0 (No
CGU_SCBF_STAT
CDU_CLKINSEL
has the programmed value.
CGU_SCBF_STAT
CDU Programming Model
and
and
4–7
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