Analog Devices ADSP-SC58 Series Hardware Reference Manual page 95

ARC4 i and j Pointer Register .............................................................................................................. 44–108
SA Command 0 ................................................................................................................................... 44–109
SA Command 1 ................................................................................................................................... 44–114
SA Inner Hash Digest Registers ........................................................................................................... 44–118
SA Key Registers .................................................................................................................................. 44–119
SA Initialization Vector Register .......................................................................................................... 44–120
SA Outer Hash Digest Registers .......................................................................................................... 44–121
SA Ready Indicator .............................................................................................................................. 44–122
SA Sequence Number Register ............................................................................................................ 44–123
SA Sequence Number Mask Registers .................................................................................................. 44–124
SA SPI Register ................................................................................................................................... 44–125
Packet Engine Source Address .............................................................................................................. 44–126
Packet Engine Status Register .............................................................................................................. 44–127
Packet Engine State Record Address .................................................................................................... 44–131
State Hash Byte Count Registers ......................................................................................................... 44–132
State Inner Digest Registers ................................................................................................................. 44–133
State Initialization Vector Registers ...................................................................................................... 44–134
Packet Engine User ID ........................................................................................................................ 44–135
Public Key Accelerator (PKA)
PKA Features ............................................................................................................................................... 45–1
PKA Functional Description........................................................................................................................ 45–1
ADSP-SC58x PKA Register List............................................................................................................... 45–2
PKA Definitions....................................................................................................................................... 45–2
PKA Architectural Concepts..................................................................................................................... 45–3
PKA Block Diagram ................................................................................................................................. 45–3
PKCP Vector Operations.......................................................................................................................... 45–4
Modular Exponentiation Operations ........................................................................................................ 45–6
Modular Inversion .................................................................................................................................. 45–13
Modular Inversion with an Even Modulus........................................................................................... 45–14
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xcv