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Port x GPIO Output Toggle Register
The
PORT_DATA_TGL
PORT_DATA_TGL
register affects the state of specific pins without impacting other pins of the port.
Reading the
PORT_DATA_TGL
the input pin/signal state.
PX15 (R/W)
Port x Bit 15 Toggle
PX14 (R/W)
Port x Bit 14 Toggle
PX13 (R/W)
Port x Bit 13 Toggle
PX12 (R/W)
Port x Bit 12 Toggle
PX11 (R/W)
Port x Bit 11 Toggle
PX10 (R/W)
Port x Bit 10 Toggle
PX9 (R/W)
Port x Bit 9 Toggle
PX8 (R/W)
Port x Bit 8 Toggle
Figure 14-10: PORT_DATA_TGL Register Diagram
Table 14-11: PORT_DATA_TGL Register Fields
Bit No.
(Access)
15
PX15
(R/W)
14
PX14
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register permits toggling the state of output GPIO pins. Setting bits in the
returns the state of the
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Toggle.
The PORT_DATA_TGL.PX15 bit toggles the output GPIO bit/pin state.
Port x Bit 14 Toggle.
The PORT_DATA_TGL.PX14 bit toggles the output GPIO bit/pin state.
PORT_DATA
register output pin state, but does not return
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 No Effect
1 Toggle Bit.
0 No Effect
1 Toggle Bit
ADSP-SC58x PORT Register Descriptions
1
0
0
0
PX0 (R/W)
Port x Bit 0 Toggle
PX1 (R/W)
Port x Bit 1 Toggle
PX2 (R/W)
Port x Bit 2 Toggle
PX3 (R/W)
Port x Bit 3 Toggle
PX4 (R/W)
Port x Bit 4 Toggle
PX5 (R/W)
Port x Bit 5 Toggle
PX6 (R/W)
Port x Bit 6 Toggle
PX7 (R/W)
Port x Bit 7 Toggle
17
16
0
0
14–25
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