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5. When this assertion occurs, the transmitter drives LP_CLK low. The transmission of the next word starts. If
the transmit buffer is empty, LP_CLK remains low until the buffer refills, regardless of the state of LP_ACK.
The LP_ACK signal can deassert when it anticipates that the buffer could fill. The receiver reasserts the LP_ACK
signal as soon as the internal DMA grant signal has occurred or the core reads the receive buffer. Either of these
actions frees a buffer location.
The LP_ACK signal inhibits transmission of the next word and not of the current byte.
NOTE:
The LP_ACK signal provides a handshake between the receiver and transmitter in the following configurations.
• When configured as a transmitter, the port drives both the data and the clock while LP_ACK is three-stated. In
this mode, LP_CLK is always synchronous with CDU0_CLKO4.
• When configured as a receiver, the link port drives the acknowledge signal and the data and clock lines are
three-stated. In this case, the external LP_CLK signal can either be synchronous or asynchronous with
CDU0_CLKO4.
• When the link port is disabled, the data, clock, and acknowledge signals are three-stated.
LPx_CLK
LPx_ACK
LPx_Dn
Figure 15-3: Link Port Communication and Handshake Waveform
The following list describes the stages shown in the Link Port Communication and Handshake Waveform figure.
1. LP_CLK stays high at byte 0 when LP_ACK is sampled low on the previous LP_CLK rising edge. LP_CLK
high indicates a stall.
2. The LP_ACK signal can deassert after byte 0.
3. The LP_ACK signal reasserts as soon as the link buffer is not full (depending on Rx FIFO conditions).
4. The transmitter samples LP_ACK to determine whether to transmit the next word.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
2
BYTE 1
BYTE 2
1
MINIMUM LACK SET-UP TIME
4
3
BYTE 3 (32-BIT)
BYTE 0 (LSBs)
5
Architectural Concepts
6
15–5
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