Analog Devices ADSP-SC58 Series Hardware Reference Manual page 353

TRU Functional Description
ADSP-SC58x TRU Register List
The Trigger Routing Unit (TRU) provides simple sequence control of distributed modules without the penalties
associated with core intervention (for example, interrupt overhead). The TRU receives trigger inputs from all master
trigger inputs (MTI) and the TRU master trigger register (TRU_MTR). Based on these inputs, the TRU logic gener-
ates trigger outputs that initiate slave operations in the processor core and peripherals. A set of registers governs
TRU operations. For more information on TRU functionality, see the TRU register descriptions.
Table 8-1: ADSP-SC58x TRU Register List
Name
TRU_ERRADDR
TRU_GCTL
TRU_MTR
TRU_SSR[n]
TRU_STAT
ADSP-SC58x TRU Interrupt List
Table 8-2: ADSP-SC58x TRU Interrupt List
Interrupt Name
ID
136 TRU0_SLV4
137 TRU0_SLV5
138 TRU0_SLV6
139 TRU0_SLV7
140 TRU0_SLV8
141 TRU0_SLV9
142 TRU0_SLV10
143 TRU0_SLV11
280 TRU0_SLV0
281 TRU0_SLV1
282 TRU0_SLV2
283 TRU0_SLV3
8–2
Description
Error Address Register
Global Control Register
Master Trigger Register
Slave Select Register
Status Information Register
Description
TRU0 Interrupt 4, Core ID = 1 only
TRU0 Interrupt 5, Core ID = 1 only
TRU0 Interrupt 6, Core ID = 1 only
TRU0 Interrupt 7, Core ID = 1 only
TRU0 Interrupt 8, Core ID = 2 only
TRU0 Interrupt 9, Core ID = 2 only
TRU0 Interrupt 10, Core ID = 2 only
TRU0 Interrupt 11, Core ID = 2 only
TRU0 Interrupt 0, Core ID = 0 only
TRU0 Interrupt 1, Core ID = 0 only
TRU0 Interrupt 2, Core ID = 0 only
TRU0 Interrupt 3, Core ID = 0 only
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity DMA
Channel
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge