Analog Devices ADSP-SC58 Series Hardware Reference Manual page 791

Sharc+ processor
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UART Functional Description
Table 17-3: ADSP-SC58x UART Interrupt List (Continued)
Interrupt
Name
ID
203
UART0_RXDMA_ERR
204
UART1_TXDMA_ERR
205
UART1_RXDMA_ERR
206
UART2_TXDMA_ERR
207
UART2_RXDMA_ERR
ADSP-SC58x UART Trigger List
Table 17-4: ADSP-SC58x UART Trigger List Masters
Trigger ID
Name
66
UART0_TXDMA
67
UART0_RXDMA
68
UART1_TXDMA
69
UART1_RXDMA
70
UART2_TXDMA
71
UART2_RXDMA
Table 17-5: ADSP-SC58x UART Trigger List Slaves
Trigger ID
Name
96
UART0_TXDMA
97
UART0_RXDMA
98
UART1_TXDMA
99
UART1_RXDMA
100
UART2_TXDMA
101
UART2_RXDMA
ADSP-SC58x UART DMA Channel List
Table 17-6: ADSP-SC58x UART DMA Channel List
DMA ID
DMA20
DMA21
17–4
Description
UART0 Receive DMA Error
UART1 Transmit DMA Error
UART1 Receive DMA Error
UART2 Transmit DMA Error
UART2 Receive DMA Error
Description
UART0 Transmit DMA
UART0 Receive DMA
UART1 Transmit DMA
UART1 Receive DMA
UART2 Transmit DMA
UART2 Receive DMA
Description
UART0 Transmit DMA
UART0 Receive DMA
UART1 Transmit DMA
UART1 Receive DMA
UART2 Transmit DMA
UART2 Receive DMA
DMA Channel Name
UART0_TXDMA
UART0_RXDMA
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity
DMA
Channel
Level
Level
Level
Level
Level
Sensitivity
Edge
Edge
Edge
Edge
Edge
Edge
Sensitivity
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Description
UART0 Transmit DMA
UART0 Receive DMA

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