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SCI Group Mask Register n
The SEC SCI group mask register (SEC_CGMSK[n]) contains selections for a group mask, an ungroup mask, and
a register lock. This register contains the system interrupt group masks for the connected core. The core uses the
SEC_CGMSK[n].UGRP and SEC_CGMSK[n].GRP fields to mask (disable) interrupts from the specified
groups.
UGRP (R/W)
Ungrouped Mask
LOCK (R/W)
Lock
Figure 7-8: SEC_CGMSK[n] Register Diagram
Table 7-7: SEC_CGMSK[n] Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
8
UGRP
(R/W)
3:0
GRP
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
SEC_CGMSK[n].LOCK bit is enabled, the
Ungrouped Mask.
The SEC_CGMSK[n].UGRP bit masks interrupts (if set) for the ungrouped inter-
rupt sources for core n.
Grouped Mask.
The SEC_CGMSK[n].GRP field selects a group of interrupt sources to mask for core
n. (For more information about interrupt source groups, see the
ister description.)
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock
1 Lock
0 Unmask Ungrouped Sources
1 Mask Ungrouped Sources
0 No groups masked
1 Mask group 0
2 Mask group 1
3 Mask groups 0, 1
ADSP-SC58x SEC Register Descriptions
2
1
0
0
0
0
GRP (R/W)
Grouped Mask
17
16
0
0
0
SEC_CGMSK[n]
register is read only.
SEC_SCTL[n]
reg-
7–27
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