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11 Static Memory Controller (SMC)
The static memory controller is a protocol converter and data transfer interface between the internal processor bus
and the external L3 memory. It provides a glueless interface to various external memories and peripheral devices,
including:
• SRAM
• ROM
• EPROM
• NOR flash memory
• FPGA/ASIC devices
The SMC acts as an SCB slave. The processor SCB interconnect fabric arbitrates accesses to the SMC. On the chip
boundary, the SMC connects to an address bus, a data bus, and signal pins for memory control (such as read, write,
output enable, and memory select lines).
SMC Features
SMC features include:
• 16-bit I/O width
• Provides flexible timing control through extended timing parameters
• Supports asynchronous access extension (SMC_ARDY pin)
• Supports 8-bit data masking writes
SMC Definitions
The timing registers contain bits to program the setup time, hold time, and access time for read and write access to
each bank separately. The SMC allows for different setup, hold, or access times for reads and writes. The
SMC_B0TIM
–
SMC_B3TIM
ing the following parameter definitions. Each of these parameters can be programmed in terms of SCLK0_0 clock
cycles.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers control the timing characteristics of the asynchronous memory interface us-
Static Memory Controller (SMC)
11–1
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