Analog Devices ADSP-SC58 Series Hardware Reference Manual page 854

• V = 1 during vertical blanking
• V = 0 when not in vertical blanking
• H = 0 at SAV
• H = 1 at EAV
• P3 = V XOR H
• P2 = F XOR H
• P1 = F XOR V
• P0 = F XOR V XOR H
P3–P0 are protection bits that enable 1-bit and 2-bit error detection, and 1-bit error correction at the receiver. The
EPPI corrects the error if it detects 1-bit errors in F, V, or H. Errors in the protection bits themselves are detected
but not corrected.
Table 18-9: Control Sequences for 8-Bit and 10-Bit ITU-R 656 Video
8-Bit Data
D9 (MSB
Preamble 1
0
0
Control Byte 1
The EPPI_STAT register contains 2 bits, EPPI_STAT.ERRDET and EPPI_STAT.ERRNCOR, that are used to
report the status of error detected and error not corrected, respectively.
The EPPI_STAT.ERRDET bit is set whenever an error is detected in the status word. However, this bit does not
generate an interrupt. The EPPI_STAT.ERRNCOR bit is set when more than a 1-bit error is detected in the status
word. An interrupt is generated when the EPPI_STAT.ERRNCOR bit is set. It can be cleared by clearing the
EPPI_STAT.ERRNCOR and EPPI_STAT.ERRDET bits. Both bits are sticky and W1C.
In many applications, video streams other than the standard NTSC/PAL formats (for example, CIF, QCIF) can be
employed. The processor interface is flexible enough to accommodate different row and field lengths. In general, as
long as the incoming video has the proper EAV/SAV codes, the EPPI can read it in. A CIF image could be format-
ted to be 656-compliant, where EAV and SAV values define the range of the image for each line. The V and F codes
are used to delimit fields and frames.
The following sections provide descriptions of EPPI operations.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
D8 D7 D6
1 1 1
0 0 0
0 0 0
F V H
D5 D4 D3
1 1 1
0 0 0
0 0 0
P3 P2 P1
ITU-R 656 Modes
10-Bit Data
D2 D1 D0
1 1 1
0 0 0
0 0 0
P0 0 0
18–15