Analog Devices ADSP-SC58 Series Hardware Reference Manual page 898

Table 18-49: EPPI_CTL Register Fields (Continued)
Bit No.
(Access)
15:14 POLS
(R/W)
13:12 POLC
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Frame Sync Polarity.
The EPPI_CTL.POLS selects whether the frame syncs' polarity is active low versus
active high.
Clock Polarity.
The EPPI_CTL.POLC selects the rising versus falling edge for sampling data and
sampling/driving syncs.
ADSP-SC58x EPPI Register Descriptions
Description/Enumeration
0 8 bits
1 10 bits
2 12 bits
3 14 bits
4 16 bits
5 18 bits
6 20 bits
7 24 bits
0 FS1 and FS2 are active high
1 FS1 is active low. FS2 is active high
2 FS1 is active high. FS2 is active low
3 FS1 and FS2 are active low
0 Clock/Sync Polarity Mode 0. For receive mode: Sample
data on falling edge and sample/drive syncs on falling
edge. For transmit mode: Drive data on rising edge and
sample/drive syncs on rising edge.
1 Clock/Sync Polarity Mode 1. For receive mode: Sample
data on falling edge and sample/drive syncs on rising
edge. For transmit mode: Drive data on rising edge and
sample/drive syncs on falling edge.
2 Clock/Sync Polarity Mode 2. For receive mode: Sample
data on rising edge and sample/drive syncs on falling
edge. For transmit mode: Drive data on falling edge and
sample/drive syncs on rising edge.
3 Clock/Sync Polarity Mode 3. For receive mode: Sample
data on rising edge and sample/drive syncs on rising
edge. For transmit mode: Drive data on falling edge and
sample/drive syncs on falling edge.
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