Table of Contents
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Serial Port (SPORT)
Features........................................................................................................................................................ 34–1
Signal Descriptions ...................................................................................................................................... 34–2
SRU Programming ...................................................................................................................................... 34–6
Functional Description ................................................................................................................................ 34–6
ADSP-SC58x SPORT Register List.......................................................................................................... 34–6
ADSP-SC58x SPORT Interrupt List ....................................................................................................... 34–7
ADSP-SC58x SPORT Trigger List ........................................................................................................... 34–9
ADSP-SC58x SPORT DMA Channel List............................................................................................. 34–10
Block Diagram........................................................................................................................................ 34–11
Architectural Concepts ........................................................................................................................... 34–12
Multiplexer Logic ................................................................................................................................ 34–13
Data Types and Companding ................................................................................................................. 34–16
Companding as a Function.................................................................................................................. 34–17
Transmit Path......................................................................................................................................... 34–17
Receive Path ........................................................................................................................................... 34–19
Operating Modes and Options .................................................................................................................. 34–19
Serial Word Length................................................................................................................................. 34–21
Clock Sample and Drive Edges ............................................................................................................... 34–21
Frame Sync Options ............................................................................................................................... 34–23
Data-Dependent versus Data-Independent Frame Syncs ..................................................................... 34–23
Support for Edge-Detected and Level-Sensitive Frame Syncs............................................................... 34–23
Early versus Late Frame Syncs ............................................................................................................. 34–24
Framed versus Unframed Frame Syncs ................................................................................................ 34–25
Frame Sync Polarity............................................................................................................................. 34–26
Premature Frame Sync Error Detection ............................................................................................... 34–26
Mode Selection ....................................................................................................................................... 34–27
Standard DSP Serial Mode .................................................................................................................. 34–27
Stereo Modes....................................................................................................................................... 34–28
2
I
S Mode.......................................................................................................................................... 34–29
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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