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ADSP-SC58x EPPI Register Descriptions
FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register
The
EPPI_FS1_WLHB
transmit mode.
In GP 1, 2 or 3 FS modes,
width required for EPPI_FS1 based on the EPPI_CLK clock.
In GP transmit mode with the EPPI_CTL.BLANKGEN bit set, this register contains the number of samples of
horizontal blanking per line. When used for blanking generation, only the lower 16 bits are valid.
Note that a value of 0 for the
EPPI_FS1_WLHB
register as containing 1.
VALUE[31:16] (R/W)
Frame Sync Width or Blanking Samples
Number
Figure 18-21: EPPI_FS1_WLHB Register Diagram
Table 18-55: EPPI_FS1_WLHB Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
18–68
register's content varies depending on whether the EPPI is in GP1/2/3 FS modes or in GP
EPPI_FS1_WLHB
EPPI_FS1_WLHB
15
0
VALUE[15:0] (R/W)
Frame Sync Width or Blanking Samples
Number
31
0
Bit Name
Frame Sync Width or Blanking Samples Number.
The EPPI_FS1_WLHB.VALUE bit field content varies depending on whether the
EPPI is in GP1/2/3 FS modes or in GP transmit mode. In GP 1, 2 or 3 FS modes, the
EPPI_FS1_WLHB.VALUE bit field is used for the generation of frame sync 1. The
register contains the width required for EPPI_FS1 based on the EPPI_CLK clock.
In GP transmit mode with EPPI_CTL.BLANKGEN set, this bit field contains the
number of samples of horizontal blanking per line.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
is used for the generation of frame sync 1. The register contains the
register is illegal. If programmed as 0, the EPPI regards the
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
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