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Status Register
The
register indicates SPI status including FIFO status, error conditions, and interrupt conditions.
SPI_STAT
When an interrupt condition from this register is unmasked (enabled) by the corresponding bit in the
register, the interrupt request is latched into the corresponding bit in the
RFS (R)
SPI_RFIFO Status
TF (R/W1C)
Transmit Finish Indication
RF (R/W1C)
Receive Finish Indication
TS (R/W1C)
Transmit Start
RS (R/W1C)
Receive Start
MF (R/W1C)
Mode Fault Indication
MMAE (R/W1C)
Memory Mapped Access Error
MMRE (R/W1C)
Memory Mapped Read Error
MMWE (R/W1C)
Memory Mapped Write Error
TFF (R)
SPI_TFIFO Full
Figure 16-35: SPI_STAT Register Diagram
Table 16-33: SPI_STAT Register Fields
Bit No.
(Access)
31
MMAE
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Memory Mapped Access Error.
The SPI_STAT.MMAE bit =1 if an attempt is made to access either the Tx or Rx
FIFO while memory-mapped access of SPI memory is enabled (see the
SPI_CTL.MMSE bit). The SPI_STAT.MMAE bit =0 when a 1 is written to it. The
SPI_STAT.MMAE bit is provided for software notification only. Its state has no fur-
ther effect.
SPI_ILAT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
23
22
21
20
19
18
17
16
0
1
0
0
0
1
0
0
Description/Enumeration
ADSP-SC58x SPI Register Descriptions
register.
SPIF (R)
SPI Finished
RUWM (R)
Receive Urgent Watermark Breached
TUWM (R)
Transmit Urgent Watermark Breached
ROR (R/W1C)
Receive Overrun Indication
TUR (R/W1C)
Transmit Underrun Indication
TC (R/W1C)
Transmit Collision Indication
TFS (R)
SPI_TFIFO Status
FCS (R)
Flow Control Stall Indication
RFE (R)
SPI_RFIFO Empty
SPI_IMSK
16–71
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